PORTS
PORT LIST Release 50 Last change 5/12/96
Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996 Ralf Brown
[This file originally by Wim Osterholt (2:512/56 or wim@djo.wtm.tudelft.nl).]
XT, AT and PS/2 I/O port addresses
Do NOT consider this information to be complete and accurate. If you want
to do hardware programming ALWAYS check the appropriate data sheets (but
even they are sometimes in error!). Be aware that erroneous port programming
can put your data or even your hardware at risk.
There are a number of memory-mapped addresses in use for I/O; see MEMORY.LST
for details on memory-mapped I/O.
---------------------------------------------
Note: the port description format is:
PPPPw RW description
where: PPPP is the four-digit hex port number
w is blank for byte-size port, 'w' for word, and 'd' for dword
R is blank or dash if not readable, 'r' if sometimes readable,
'R' if "always" readable, '?' if readability unknown
W is blank or dash if not writable, 'w' if sometimes writable,
'W' if "always" writable, '?' if writability unknown
----------P0000001F--------------------------
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
0000 RW DMA channel 0 address byte 0, then byte 1
0001 RW DMA channel 0 word count byte 0, then byte 1
0002 RW DMA channel 1 address byte 0, then byte 1
0003 RW DMA channel 1 word count byte 0, then byte 1
0004 RW DMA channel 2 address byte 0, then byte 1
0005 RW DMA channel 2 word count byte 0, then byte 1
0006 RW DMA channel 3 address byte 0, then byte 1
0007 RW DMA channel 3 word count byte 0, then byte 1
0008 R DMA channel 0-3 status register (see #P001)
0008 W DMA channel 0-3 command register (see #P002)
0009 W DMA channel 0-3 write request register (see #P003)
000A RW DMA channel 0-3 mask register (see #P004)
000B W DMA channel 0-3 mode register (see #P005)
000C W DMA clear byte pointer flip-flop
000D R DMA read temporary register
000D W DMA master clear
000E W DMA clear mask register
000F W DMA write mask register
Bitfields for DMA channel 0-3 status register:
Bit(s) Description (Table P001)
7 channel 3 request active
6 channel 2 request active
5 channel 1 request active
4 channel 0 request active
3 channel terminal count on channel 3
2 channel terminal count on channel 2
1 channel terminal count on channel 1
0 channel terminal count on channel 0
SeeAlso: #P002,#P078
Bitfields for DMA channel 0-3 command register:
Bit(s) Description (Table P002)
7 DACK sense active high
6 DREQ sense active high
5 =1 extended write selection
=0 late write selection
4 rotating priority instead of fixed priority
3 compressed timing
2 =1 enable controller
=0 enable memory-to-memory
1-0 channel number
SeeAlso: #P001,#P004,#P005,#P079
Bitfields for DMA channel 0-3 request register:
Bit(s) Description (Table P003)
7-3 reserved (0)
2 =0 clear request bit
=1 set request bit
1-0 channel number
00 channel 0 select
01 channel 1 select
10 channel 2 select
11 channel 3 select
SeeAlso: #P004
Bitfields for DMA channel 0-3 mask register:
Bit(s) Description (Table P004)
7-3 reserved (0)
2 =0 clear mask bit
=1 set mask bit
1-0 channel number
00 channel 0 select
01 channel 1 select
10 channel 2 select
11 channel 3 select
SeeAlso: #P001,#P002,#P003,#P080
Bitfields for DMA channel 0-3 mode register:
Bit(s) Description (Table P005)
7-6 transfer mode
00 demand mode
01 single mode
10 block mode
11 cascade mode
5 direction
=0 address increment select
=1 address decrement select
3-2 operation
00 verify operation
01 write to memory
10 read from memory
11 reserved
1-0 channel number
00 channel 0 select
01 channel 1 select
10 channel 2 select
11 channel 3 select
SeeAlso: #P002,#P081
----------P0010001F--------------------------
PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
----------P0018------------------------------
PORT 0018 - PS/2 - EXTENDED FUNCTION REGISTER
0018 -W PS/2 extended function register
----------P001A------------------------------
PORT 001A - PS/2 - EXTENDED FUNCTION EXECUTE
----------P0020003F--------------------------
PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7"
0020 -W PIC initialization command word ICW1 (see #P006)
0020 -W PIC output control word OCW2 (see #P011)
0020 -W PIC output control word OCW3 (see #P012)
0020 R- PIC interrupt request/in-service registers after OCW3
request register:
bit 7-0 = 0 no active request for the corresponding int. line
= 1 active request for corresponding interrupt line
in-service register:
bit 7-0 = 0 corresponding line not currently being serviced
= 1 corresponding int. line currently being serviced
0021 -W PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P007,#P008,#P009)
0021 RW PIC master interrupt mask register OCW1 (see #P010)
Bitfields for PIC initialization command word ICW1:
Bit(s) Description (Table P006)
7-5 0 (only used in 8080/8085 mode)
4 ICW1 is being issued
3 (LTIM)
=0 edge triggered mode
=1 level triggered mode
2 interrupt vector size
=0 successive interrupt vectors use 8 bytes (8080/8085)
=1 successive interrupt vectors use 4 bytes (80x86)
1 (SNGL)
=0 cascade mode
=1 single mode, no ICW3 needed
0 ICW4 needed
SeeAlso: #P007,#P008,#P009
Bitfields for PIC initialization command word ICW2:
Bit(s) Description (Table P007)
7-3 address lines A0-A3 of base vector address for PIC
2-0 reserved
SeeAlso: #P006,#P008,#P009
Bitfields for PIC initialization command word ICW3:
Bit(s) Description (Table P008)
7-0 =0 slave controller not attached to corresponding interrupt pin
=1 slave controller attached to corresponding interrupt pin
SeeAlso: #P006,#P007,#P009
Bitfields for PIC initialization command word ICW4:
Bit(s) Description (Table P009)
7-5 reserved (0)
4 running in special fully-nested mode
3-2 mode
0x nonbuffered mode
10 buffered mode/slave
11 buffered mode/master
1 Auto EOI
0 =0 8085 mode
=1 8086/8088 mode
SeeAlso: #P006,#P007,#P008
Bitfields for PIC output control word OCW1:
Bit(s) Description (Table P010)
7 disable IRQ7 (parallel printer interrupt)
6 disable IRQ6 (diskette interrupt)
5 disable IRQ5 (fixed disk interrupt)
4 disable IRQ4 (serial port 1 interrupt)
3 disable IRQ3 (serial port 2 interrupt)
2 disable IRQ2 (video interrupt)
1 disable IRQ1 (keyboard, mouse, RTC interrupt)
0 disable IRQ0 (timer interrupt)
SeeAlso: #P011,#P012,#P077
Bitfields for PIC output control word OCW2:
Bit(s) Description (Table P011)
7-5 operation
000 rotate in auto EOI mode (clear)
001 (WORD_A) nonspecific EOI
010 (WORD_H) no operation
011 (WORD_B) specific EOI
100 (WORD_F) rotate in auto EOI mode (set)
101 (WORD_C) rotate on nonspecific EOI command
110 (WORD_E) set priority command
111 (WORD_D) rotate on specific EOI command
4 reserved (0)
3 reserved (0)
2-0 interrupt request to which the command applies
(only used by WORD_B, WORD_D, and WORD_E)
SeeAlso: #P010,#P012
Bitfields for PIC output control word OCW3:
Bit(s) Description (Table P012)
7 reserved (0)
6-5 special mask
0x no operation
10 reset special mask
11 set special mask
4 reserved (0)
3 reserved (1)
2 poll command
1-0 function
0x no operation
10 read interrupt request register on next read from port 0020
11 read interrupt in-service register on next read from port 0020
SeeAlso: #P010,#P011
----------P00220023--------------------------
PORT 0022-0023 - CHIP SET DATA
0022 -W index for accesses to data port
0023 RW chip set data
----------P00220023--------------------------
PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS
0022 -W index for accesses to next port (see #P013)
0023 RW cache configuration register array (indexed by port 0022h)
(Table P013)
Values for Cyrix Cx486SLC/DLC Cache Configuration register number:
C0h CR0 (see #P015)
C1h CR1 (see #P016)
C4h non-cacheable region 1, start address bits 31-24
C5h non-cacheable region 1, start address bits 23-16
C6h non-cacheable region 1, start addr 15-12, size (low nibble) (see #P014)
C7h non-cacheable region 2, start address bits 31-24
C8h non-cacheable region 2, start address bits 23-16
C9h non-cacheable region 2, start addr 15-12, size (low nibble) (see #P014)
CAh non-cacheable region 3, start address bits 31-24
CBh non-cacheable region 3, start address bits 23-16
CCh non-cacheable region 3, start addr 15-12, size (low nibble) (see #P014)
CDh non-cacheable region 4, start address bits 31-24
CEh non-cacheable region 4, start address bits 23-16
CFh non-cacheable region 4, start addr 15-12, size (low nibble) (see #P014)
(Table P014)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
00h disabled
01h 4K
02h 8K
03h 16K
04h 32K
05h 64K
06h 128K
07h 256K
08h 512K
09h 1M
0Ah 2M
0Bh 4M
0Ch 8M
0Dh 16M
0Eh 32M
0Fh 4G
SeeAlso: #P013
Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s) Description (Table P015)
0 "NC0" first 64K of each 1M noncacheable in real/V86
1 "NC1" 640K-1M noncacheable
2 "A20M" enables A20M# input pin
3 "KEN" enables KEN# input pin
4 "FLUSH" enables KEN# input pin
5 "BARB" enables internal cache flushing on bus holds
6 "C0" cache direct-mapped instead of 2-way associative
7 "SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P013,#P016
Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s) Description (Table P016)
0 "RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P013,#P015
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
0022 -W index for accesses to next port (see #P017)
0023 RW configuration control register array (indexed by port 0022h)
(Table P017)
Values for Cyrix 5x86 configuration registers:
20h Performance Control (see #P022)
C0h
C1h Configuration Control #1 (CCR1) (see #P018)
C2h Configuration Control #2 (CCR2) (see #P019)
C3h Configuration Control #3 (CCR3) (see #P020)
C4h Configuration Control #4 (CCR4) (see #P021)
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh System Memory Management address region #0 (smar0) (see #P023)
CEh System Memory Management address region #1 (smar1)
CFh System Memory Management address region #2 (smar2)
F0h Power Management (see #P024)
FEh R Device Identification #0
CPU device ID
FFh R Device Identification #1
bits 3-0: revision
bits 7-4: stepping
Note: accesses to indices other than 20h,C0h-CFh, or F0h-FFh generate
external I/O cycles
Bitfields for Cyrix 5x86 Configuration Control Register 1 (CCR1):
Bit(s) Description (Table P018)
0 reserved
1 enable SMM pins
2 system management memory access
3 main memory access
7-4 reserved
SeeAlso: #P019,#P020,#P021
Bitfields for Cyrix 5x86 Configuration Control Register 2 (CCR2):
Bit(s) Description (Table P019)
0 reserved
1 enable write-back cache interface pins
2 lock NW bit
3 suspend on HLT instruction
4 write-through region 1
5 reserved
6 enable burst write cycles
7 enable suspend pins
SeeAlso: #P018,#P020,#P021
Bitfields for Cyrix 5x86 Configuration Control Register 3 (CCR3):
Bit(s) Description (Table P020)
0 SMM register lock
1 NMI enable
2 linear address burst cycles
3 SMM mode
7-4 map enable (0001 to enable several configuration registers)
SeeAlso: #P018,#P019,#P021,#P022,#P024
Bitfields for Cyrix 5x86 Configuration Control Register 4 (CCR4):
Bit(s) Description (Table P021)
2-0 I/O recovery time
3 enable memory-read bypassing
4 enable directory table entry cache
6-5 reserved
7 enable CPUID instruction (stepping 1+ and Cx6x86)
Note: this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P018,#P019,#P020
Bitfields for Cyrix 5x86 Performance Control register:
Bit(s) Description (Table P022)
0 return stack enabled
1 branch-target buffer enabled
2 loop enable
6-3 reserved (0)
7 load-store serialization enabled
Note: this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P024,#P018
Bitfields for Cyrix 5x86 SMM Address Region register:
Bit(s) Description (Table P023)
3-0 block size
23-4 starting address
Bitfields for Cyrix 5x86 Power Management register:
Bit(s) Description (Table P024)
1-0 core clock to bus clock ratio
2 CPU running at half bus speed
Note: this register is only accessible when bits 7-4 of CCR3 are 0001
--------X-P00220023--------------------------
PORT 0022-0023 - 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER
Notes: this chip uses a chip ID of 01
the LIM register herein use a chip ID of 1A
0022 -W index for accesses to data port (see #P025)
0023 RW chip set data
(Table P025)
Values for 82359 DRAM controller register index:
00h bank 0
bit 7 unknown
bit 6-4 000 DRAM in bank 0 (standard)
001 bank 1
010 bank 2
011 bank 3
100 banks 0,1
101 banks 2,3
110 banks 0,1,2,3
111 empty (standard for 1,2,3)
bit 3-2 unknown
bit 1-0 00 64K chips used
01 256K
10 1M
11 4M
01h bank 1
02h bank 2
03h bank 3
21h chip ID register
----------P00220023--------------------------
PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)
0022 RW chip set data
0023 ?W index for accesses to data port (see #P026)
(Table P026)
Values for Etec Cheetah ET6000 chip set register index:
10h system configuration register (see #P027)
11h cache configuration & non-cacheable block size register (see #P028)
12h non-cacheable block address register
bit 7-1 non-cacheable address, A25-A19
bit 0 reserved
13h DRAM bank & type configuration register (see #P029)
14h DRAM configuration register (see #P030)
15h shadow RAM configuration register (see #P031)
Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s) Description (Table P027)
7-6 00 turbo/non-turbo
01 local device supported
10 suspend mode
11 illegal
5 reserved
4 refresh selection
0 = AT type refresh
1 = concurrent refresh
3 slow refresh 95mSec enabled
2 fast reset delay
0 = do not use delay
1 = wait for 2mSec delay
1 wait for HALT after KBDRST
0 RAM at A0000-BFFFF
0 = AT bus cycle
1 = local bus cycle
SeeAlso: #P026
Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s) Description (Table P028)
7-5 000 disabled
001 512K
010 1M
011 2M
100 4M
101 8M
110 16M
111 32M
4 DRAM banks
0 = 2-bank DRAM
1 = 4-bank DRAM
3-0 reserved
SeeAlso: #P026
Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register:
Bit(s) Description (Table P029)
7-6 bank 3 DRAM type
00 none
01 256K
10 1M
11 4M
5-4 bank 2 DRAM type
3-2 bank 1 DRAM type
1-0 bank 0 DRAM type
SeeAlso: #P026
Bitfields for Etec Cheetah ET6000 DRAM configuration register:
Bit(s) Description (Table P030)
7 on-board memory range 15M to 16M disabled
6 on-board memory range 512K-640K disabled
5 ROM chip select at C0000-DFFFF enabled
4 RAS to CAS time
0 = 1 SYSCLCK, not for R0WS
1 = 2 SYSCLCK
3 RAS precharge time
0 = 1.5 SYSCLCK
1 = 2.5 SYSCLCK
2-1 read cycle wait state
00 = 0 wait state
01 = 1 ws
10 = 2 ws
11 = 3 ws
0 write cycle wait state
0 = 0 ws
1 = 1 ws
SeeAlso: #P026
Bitfields for Etec Cheetah ET6000 shadow RAM configuration register:
Bit(s) Description (Table P031)
7 shadow at C0000-FFFFF
0 = non-cacheable
1 = cacheable and cache-write-proteced
6 access ROM/RAM at F0000-FFFFF
0 = read from ROM, write to RAM
1 = read from shadow, write is protected
5 access ROM/RAM at E0000-EFFFF
0 = access on-board ROM, AT bus cycle
1 = access shadow E0000-EFFFF enabled
4 RAM at E0000-EFFFF is read-only
3 access ROM/RAM at D0000-DFFFF
0 = access on-board ROM, AT bus cycle
1 = access shadow D0000-DFFFF enabled
2 RAM at D0000-DFFFF is read-only
1 access ROM/RAM at C0000-CFFFF
0 = access on-board ROM, AT bus cycle
1 = access shadow C0000-CFFFF enabled
0 RAM at C0000-CFFFF is read-only
SeeAlso: #P026
----------P00220023--------------------------
0022-0023 ---- Hewlett-Packard Hornet chipset (HP 100LX/200LX)
0022 RW index for accesses to data port (see Table P189)
0023 RW chip set data
(Table P032)
Values for HP Hornet chipset register index:
1Eh buzzer volume/clock oscillator speed
bit 7-6: buzzer volume
bit 5-4: system oscillator speed
00: 10.738636MHz
01: 15.836773MHz(HP 100/200LX has oscillator with this speed)
10: 21.477272MHz
11: 31.673550MHz
21h display timing???
23h LCD contrast (see INT15h AH=62h)
valid values: 00h-1fh (1fh is the darkest)
51h power adapter status
bit 7-1: ???
bit 0: power adapter status(0=inactive/1=active)
52h nicad charge status
bit 7-3: ???
bit 2: battery charging status(0=???/1=slow charge)
bit 1-0: ???
53h nicad charge status
bit 7-1: ???
bit 0: battery charging status(0=???/1=fast charge)
80h memory wait for internal ROM
valid values: 00h-07h
81h memory wait for internal RAM
valid values: 00h-03h
82h memory wait for external RAM
valid values: 00h-0fh
87h battery status???
----------P00220024--------------------------
PORT 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips
0022 ?W index for accesses to data port
0024 RW chip set data
----------P00220025--------------------------
PORT 0022-0025 - INTEL 82360SL CHIPSET (FOR 386SL)
0022 -W CPU write mode register
0023 R- configuration status register
bit 7: 82360 configuration is open
0024 -W 82360 configuration index
0025 RW 82360 configuration data
Bitfields for Intel 82360SL CPU write mode register:
Bit(s) Description (Table P033)
0 unlock configuration space
1 enable selected unit
3-2 unit
00 memory configuration
01 cache
10 internal bus
11 external bus
----------P0022002B--------------------------
PORT 0022-002B - INTEL 82355, PART OF CHIPSET FOR 386sx
Note: initialisation in POST will disable these addresses, only a hard
reset will enable them again.
0022w RW 82335 MCR memory configuration register (if LOCK=0) (see #P034)
0024w RW 82335 RC1 roll compare register (if LOCK=0) (see #P035)
0026w RW 82335 RC2 roll compare register (if LOCK=0) (see #P035)
0028w RW 82335 CC0 address range compare register (if LOCK=0) (see #P036)
002Aw RW 82335 CC1 address range compare register (if LOCK=0) (see #P036)
Bitfields for 82335 MCR memory configuration register:
Bit(s) Description (Table P034)
15-12 reserved
11 "VRO" video read only (0=r/w, 1=r/o)
10 "EN#"
0=enable video RAM accesses (A0000h-8FFFFh)
1=disable accesses
9 "ENADP#"
0=enable adapter ROM accesses (C0000h-8FFFFh)
1=disable adapter ROM accesses, shadow enabled
8 "ROMSIZE" 0=256KB ROM, 1=512KB ROM
7-6 "INTERL" memory interleaving
00 = 1 memory bank installed (no interleave)
01 = 2 memory banks installed
10 = 3 memory banks installed
11 = 4 memory banks installed
5 reserved
4 "DSIZE" 0=1MBx1DRAMs, 1=256KBx1 or 256KBx4 DRAMs
3 "S640" base memory size is 0=512KB, 1=640KB
2-1 reserved
0 "ROMEN#" ROM enable
0 enable BIOS ROM accesses (E0000h-FFFFFh)
1 disable BIOS ROM accesses, enable shadow
Note: One of the remaining reserved bits is the LOCK bit, which will be set
during power on, disabling access to the 82335s registers.
Bitfields for 82335 roll compare register:
Bit(s) Description (Table P035)
15-9 selects address range to be remapped (C23-C17)
8 reserved
7-1 selects address bits to be included in re-mapping comparision (M23-M17)
0 "EN" enables roll address mapping
Bitfields for 82335 address range compare register:
Bit(s) Description (Table P036)
15-11 specifies top of address range (C23-C19)
10-8 reserved
7-3 selects address bits to be included in address range comparision
(M23-M19)
2-1 reserved
0 "EN" enable address range comparision
----------P00240028--------------------------
PORT 0024-0028 - HEADLAND HTK340 SHASTA 386/486 CHIPSET
0024 Rw data port
0028 ?W index port to chipset registers (see #P037,#P038)
(Table P037)
Values for Headland HT321 register index:
00h R chip/revision,read-only
bit7-4: reserved (=0)
bit3-0: chip revision, 0=A, 1=B, 3=D
01h RW system clocking (default=00h)
bit7-4: reserved (=0)
bit3-0: ISA speed set
02h RW system parameters (default=00h) (see #P039)
04h RW co-processor (default=00h)
bit7-3: reserved (=0)
bit2=1: soft-NPU reset blocked (386 only)
bit1=1: weitek installed
bit0=1: 387 installed
06h RW DMA (default=00h) (see #P040)
07h RW EPROM (default=00h) (see #P041)
08h RW I/O and memory map holes (default=00h)
bit7-4: reserved (=0)
bit3 : 0/1 I/O map hole-A
bit2 : reserved (=0)
bit1 : 0/1 memory map hole-B
bit0 : reserved (=0)
10h RW hole-A low address (default=00h)
11h RW hole-A high address (default=00h)
19h RW mem hole-B start address, lower (default=00h)
1Ah RW mem hole-B start address, higher (default=00h)
bit7-6: reserved (=0)
bit5-0: address of mem hole-B start
1Ch RW mem hole-B end address, lower (default=00h)
1Dh RW mem hole-B end address, higher (default=00h)
bit7-6: reserved (=0)
bit5-0: address of mem hole-B end
SeeAlso: #P038
(Table P038)
Values for Headland HT342 register index:
20h R identifier port read
bit7-4: DRAM controller identifier (0010b)
bit3-0: revision number (0=A)
21h R feature port read (default=00h)
24h RW DRAM options port #1 (default=00h)
bit7 : 0/1 staggered refresh
bit6 : refresh type
bit5 : 0/1 DRAM paging
bit4-2: CAS interleave
bit1-0: banks
25h DRAM options port #2 (default=00h)
bit7-6: DRAM bank 1 type
bit5-4: DRAM bank 2 type
bit3-2: DRAM bank 1?? type
bit1-0: DRAM bank 0 type
26h RW DRAM options port #3 (default=FFh) (see #P042)
27h RW DRAM options port #4 (default=FFh) (see #P043)
28h RW data transfer control port (default=00h)
doubled indexed registers (28h-2Ah)
bit7 : initiate transfer
bit6 : read/write transfer
bit5-4: reserved
bit3-0: transfer/destination
29h RW RAM address register (default=00h)
doubled indexed registers (28h-2Ah)
bit7-5: reserved
bit4-0: RAM address registers contents
2Ah RW data transfer port (default=00h)
doubled indexed registers (28h-2Ah)
bit7-6: reserved
bit5 : EMS translation
bit4 : reserved
bit3 : 0/1 cacheing
bit2 : 0/1 write
bit1 : 0/1 read
bit0 : 0/1 shadow
2Bh RW other options (default=00h) (see #P044)
2Dh RW DRAM options port #5 (default=03h)
bit7-5: reserved
bit4 : 0/1 10æs RAS timeout
bit3-2: BUS speed
bit1-0: BUS recovery for DRAM cycles
00b=0: 4-1-1-1 10b=0.5
01b=1: 4-2-2-2 11b=1??
82h read transfer
C2h write transfer
SeeAlso: #P037
Bitfields for Headland HT321 register 02h (system parameters):
Bit(s) Description (Table P039)
7-6 IO recovery time (rev. D+)
5 parity override
4-3 cycle-width
2 0/1 port 92 functionality
1 IO decode
0 0/1 posted backplane MEMWN cycles
SeeAlso: #P037
Bitfields for Headland HT321 register 06h (DMA control):
Bit(s) Description (Table P040)
7 reserved (=0)
6 1/0 IOCHRDY during master cycle (rev. C+)
5 0/1 fast sample DMA
4-3 DMA waitstate 00b=3 .. 11b=0
2 0/1 DMA flow-through mode
1 0/1 extended DMA page register
0 DMA clock
SeeAlso: #P037
Bitfields for Headland HT321 register 07h (EPROM control):
Bit(s) Description (Table P041)
7-6 reserved (=0)
5 0/1 EADS CACHE invalidation for EPROM writes (rev. D+)
4 0/1 ROMEN for EPROM writes (rev. C+)
3 0/1 middle BIOS region of 64KB space below 16MB
2 ROM-size (0=64KB, 1=128KB)
1 V-BIOS-add (0=separate, 1=same device)
0 ROM-access time (0=250ns, 1=125ns)
SeeAlso: #P037
Bitfields for Headland HT342 register 26h (DRAM CAS control):
Bit(s) Description (Table P042)
7 CAS hold on RAS (CAS before RAS refresh)
6 CAS precharge
5 CAS burst delay
4 CAS delay (writes)
3 CAS delay (reads)
2 CAS active time (writes)
1-0 CAS active time (reads)
SeeAlso: #P038,#P043
Bitfields for Headland HT342 register 27h (DRAM RAS control):
Bit(s) Description (Table P043)
7 RAS delay
6-5 RAS active (writes)
4-2 RAS active (reads)
1-0 RAS precharge
SeeAlso: #P038,#P042
Bitfields for Headland HT342 register 2Bh (other options):
Bit(s) Description (Table P044)
7 reserved
6 0/1 middle BIOS
5 0/1 data pipeline
4 0/1 data pipeline
3 IO-decode
2 reserved
1 16bit DMA bridge
0 0/1 write buffering
SeeAlso: #P038
----------P00260027--------------------------
PORT 0026-0027 - POWER MANAGEMENT
0026 -W index for data port
0027 RW power management data
----------P002E002F--------------------------
PORT 002E-002F - DELL ENHANCED PARALLEL PORT
SeeAlso: PORT 015Ch,PORT 026Eh,PORT 0398h
002E -W index for data port (see #P045)
002F RW EPP command data
(Table P045)
Values for Dell Enhanced Parallel Port register index:
00h bit 0: ???
02h bit 7: port in bidirectional mode
04h bits 0 and 2: ECP/EPP mode control
----------P0038003F--------------------------
PORT 0038-003F - PC radio by CoZet Info Systems
Notes: The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
All of these addresses show a readout of FF in initial state.
Once started, all of the addresses show FB, whatever might happen.
----------P0040005F--------------------------
PORT 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254)
Note: XT & AT use ports 40h-43h; PS/2 uses ports 40h, 42h-44h, and 47h
0040 RW PIT counter 0, counter divisor (XT, AT, PS/2)
0041 RW PIT counter 1, RAM refresh counter (XT, AT)
don't set below 3 on PCs (default 12h)
0042 RW PIT counter 2, cassette & speaker (XT, AT, PS/2)
During normal operation mode (8253) 40h-42h set the counter values on
write and get the current counter value on read. In 16bit modes two
consequtive writes/reads must be issued, first with the low byte,
followed by the high byte. In 8254 read back modes, all selected
counters and status are latched and must be read out completely
before normal operation is valid again. Each counter switches back
to normal operation after read out. In 'get status and counter'
mode the first byte read is the status, followed by one or two
counter values. (see #P046)
0043 RW PIT mode port, control word register for counters 0-2 (see #P047)
Once a control word has been written (43h), it must be followed
immediately by performing the corresponding action to the counter
registers (40h-42h), else the system may hang!!
0044 RW PIT counter 3 (PS/2, EISA)
used as fail-safe timer. generates an NMI on time out.
for user generated NMI see at 0462.
0047 -W PIT control word register counter 3 (PS/2, EISA)
bit 7-6 = 00 counter 3 select
= 01 reserved
= 10 reserved
= 11 reserved
bit 5-4 = 00 counter latch command counter 3
= 01 read/write counter bits 0-7 only
= 1x reserved
bit 3-0 = 00
0048 ?? EISA
0049 ?? 8254 timer 2, not used (counter 1)
004A ?? EISA programmable interval timer 2
004B ?? EISA programmable interval timer 2
Bitfields for 8254 PIT counter status byte:
Bit(s) Description (Table P046)
7 PIN status of OUTx Pins (1=high, 0=low)
6 counter start value loaded
=0: yes, so counter latch is valid to be read
=1: no, wait for counter latch to be set (may last a while)
5-0 counter mode, same as bit5-0 at 43h
SeeAlso: #P047
Bitfields for 8253/8254 PIT mode control word:
Bit(s) Description (Table P047)
7-6 counter select
00 counter 0 select
01 counter 1 select (not PS/2)
10 counter 2 select
11 (8253) reserved
(8254) read back counter (see #P046)
---if counter select---
5-4 counter access
00 counter latch command
BUG: Intel Neptune/Mercury Chipset 8237IB (SIO) needs a
short delay after issueing this command, else the
MSB may be outdated concerning the LSB, resulting
in large measuring errors.
Workaround: Check for this condition by comparing
results with last results and don't use errornous
results.
01 read/write counter bits 0-7 only
10 read/write counter bits 8-15 only
11 read/write counter bits 0-7 first, then 8-15
3-1 counter mode
000 mode 0 select - zero detection interrupt
001 mode 1 select - programmable one shot
x10 mode 2 select - rate generator
x11 mode 3 select - square wave generator
divisor factor 3 not allowed!
100 mode 4 select - software triggered strobe
101 mode 5 select - hardware triggered strobe
0 counting style
0 binary counter 16 bits
1 BCD counter (4 decades)
---if read back---
5-4 what to read
00 reserved
01 counter status
10 counter value
11 counter status and value
3 select counter 2
2 select counter 1
1 select counter 0
0 reserved (0)
Note: after issuing a read back 'get status' command, any new read back
command is ignored until the status is read from all selected
counters.
----------P0060006F--------------------------
PORT 0060-006F - KEYBOARD CONTROLLER 804x (8041, 8042) (or PPI (8255) on PC,XT)
Note: XT uses ports 60h-63h, AT uses ports 60h-64h
0060 RW KB controller data port or keyboard input buffer (ISA, EISA)
should only be read from after status port bit0 = 1
should only be written to if status port bit1 = 0
0060 R- KeyBoard or KB controller data output buffer (via PPI on XT)
PC: input from port A of 8255, if bit7 in 61h set (see #P063)
get scancodes, special codes (in PC: with bit7 in 61h cleared)
(see #P057)
0061 R- KB controller port B control register (ISA, EISA)
system control port for compatibility with 8255 (see #P060)
0061 -W KB controller port B (ISA, EISA) (PS/2 port A is at 0092)
system control port for compatibility with 8255 (see #P059)
0061 -W PPI Programmable Peripheral Interface 8255 (XT only)
system control port (see #P061)
0062 RW PPI (XT only) data port C (see #P062)
0063 RW PPI (XT only) command mode register (see #P064)
0064 R- keyboard controller read status (see #P065,#P066,#P067)
0064 -W keyboard controller input buffer (ISA, EISA) (see #P068)
0064 -W (Amstrad/Schneider PC1512) set 'DIP switch S1' setting
stored in CMOS RAM that PPI should report for compatibility
0065 -W (Amstrad/Schneider PC1512) set 'DIP switch S2' RAM size setting
stored in CMOS RAM, that PPI port C (PORT 0064h) should report for
compatibility
0065 R- communications port (Olivetti M24)
0068 -W (HP-Vectra) control buffer (HP commands) (see #P069)
0069 R- (HP-Vectra) SVC (keyboard request SerViCe port)
006A -W (HP-Vectra) Acknowledge (clear processing, done)
006C-006F HP-HIL (Human Interface Link = async. serial inputs 0-7)
Bitfields for AT keyboard controller input port:
Bit(s) Description (Table P048)
7 keyboard enabled
6 =0 CGA, else MDA
5 =0 manufacturing jumper installed
4 =0 system RAM 512K, else 640K
3-0 reserved
SeeAlso: #P049,#P051
Bitfields for AT keyboard controller input port (Compaq):
Bit(s) Description (Table P049)
7 security lock is unlocked
6 =0 Compaq dual-scan display, 1=non-Compaq display
5 system board dip switch 5 is OFF
4 =0 auto speed selected, 1=high speed selected
3 =0 slow (4MHz), 1 = fast (8MHz)
2 no math coprocessor installed
1-0 reserved
SeeAlso: #P050
Bitfields for AT keyboard controller output port:
Bit(s) Description (Table P050)
7 keyboard data output
6 keyboard clock output
5 input buffer NOT full
4 output buffer NOT empty
3 reserved (see note)
2 reserved (see note)
1 gate A20
0 system reset
Note: bits 2 and 3 are the turbo speed switch or password lock on
Award/AMI/Phoenix BIOSes. These bits make use of nonstandard
keyboard controller BIOS functionality to manipulate
pin 23 (8041 port 22) as turbo switch for AWARD
pin 35 (8041 port 15) as turbo switch/pw lock for Phoenix
SeeAlso: #P048,#P051
Bitfields for HP Vectra keyboard controller output port:
Bit(s) Description (Table P051)
7-5 reserved
4 output buffer full (OBF) interrupt
3 HP SVC interrupt
2 HP-HIL controller AutoPoll
1 A20 gate
0 system reset
SeeAlso: #P050,#P052
Bitfields for HP Vectra command byte:
Bit(s) Description (Table P052)
7 reserved (0)
6 scancode conversion mode (1 = PC/XT, 0 = PC/AT)
5 unused
4 disable keyboard (unless bit 3 set)
3 override keyboard disable
2 System Flag (may be read from port 0060h)
1 reserved
0 OBF interrupt enable
SeeAlso: #P051
(Table P053)
Values for keyboard commands (data also goes to PORT 0060h):
Value Count Description
EDh double set/reset mode indicators Caps Num Scrl
bit 2 = CapsLk, bit 1 = NumLk, bit 0 = ScrlLk
all other bits must be zero.
EEh sngl diagnostic echo. returns EEh.
EFh sngl NOP (No OPeration). reserved for future use
EF+26h double [Cherry MF2 G80-1501HAD] read 256 bytes of chipcard data
keyboard must be disabled before this and has to
be enabled after finished.
F0h double get/set scan code set
00h get current set
01h scancode set 1 (PCs and PS/2 mod 30, except Type 2 ctrlr)
02h scancode set 2 (ATs, PS/2, default)
03h scancode set 3
F2h sngl read keyboard ID (read two ID bytes)
AT keyboards returns FA (ACK)
MF2 returns AB 41 (translation) or
AB 83 (pass through)
F3h double set typematic rate/delay
format of the second byte:
bit7=0 : reserved
bit6-5 : typemativ delay
00b=250ms 10b= 750ms
01b=500ms 11b=1000ms
bit4-0 : typematic rate (see #P058)
F4h sngl enable keyboard
F5h sngl disable keyboard. set default parameters (no keyboard scanning)
F6h sngl set default parameters
F7h sngl [MCA] set all keys to typematic (scancode set 3)
F8h sngl [MCA] set all keys to make/release
F9h sngl [MCA] set all keys to make only
FAh sngl [MCA] set all keys to typematic/make/release
FBh sngl [MCA] set al keys to typematic
FCh double [MCA] set specific key to make/release
FDh double [MCA] set specific key to make only
FEh sngl resend last scancode
FFh sngl perform internal power-on reset function
Note: each command is acknowledged by FAh (ACK), if not mentioned otherwise.
See PORT 0060h-R for details.
SeeAlso: #P054
(Table P054)
Values for Mouse functions (for PS/2-like pointing devices):
Value Count Description
E6h sngl set mouse scaling to 1:1
E7h sngl set mouse scaling to 2:1
E8h double set mouse resolution
(00h=1/mm, 01h=2/mm, 02h=4/mm, 03h=8/mm)
E9h sngl get mouse information
read two status bytes:
byte 0: flags (see #P055)
byte 1: resolution
EAh sngl set mouse to stream mode (mouse sends data on any changes)
EBh sngl get mouse data (from mouse to controller) (see #P056)
on reading, each data packet consists of 8 bytes:
ECh sngl reset mouse wrap mode (to normal mode)
EEh sngl set wrap mode
F0h sngl set remote mode (instead of stream mode), mouse sends data
only on issueing command EBh.
F2h sngl read mouse ID (read one, two?? ID bytes)
00h=mouse
F3h double set mouse sample rate in reports per second
0Ah=10/s 50h= 80/s
14h=20/s 64h=100/s
28h=40/s C8h=200/s
3Ch=60/s
F4h sngl enable mouse (in stream mode)
F5h sngl disable mouse (in steam mode), set default parameters
F6h sngl reset to defaults: 100/s, scaling 1:1, stream-mode, 4/mm,
disabled
FEh sngl resend last mouse data (8 bytes, see EBh)
FFh sngl reset mouse
Notes: must issue command D4h to port 64h first to access mouse functions
all commands except ECh and FFh are acknowledged by FAh (ACK) or
FEh (Resend); get mouse ID (F2h) returns mouse ID.
SeeAlso: #P053
Bitfields for mouse status byte 0:
Bit(s) Description (Table P055)
7 unused
6 remote rather than stream mode
5 mouse enabled
4 scaling set to 2:1
3 unused
2 left button pressed
1 unused
0 right button pressed
SeeAlso: #P054,#P056
Format of mouse data packet:
Offset Size Description (Table P056)
00h BYTE status
bit7 : y-data overrun
bit6 : x-data overrun
bit5 : y-data negative
bit4 : x-data negative
bit3-2=0: reserved
bit1 : right button pressed
bit0 : left button pressed
01h BYTE reserved
02h BYTE x-data
03h BYTE reserved
04h BYTE y-data
05h BYTE reserved
06h BYTE z-data (0)
07h BYTE reserved
SeeAlso: #P054,#P055
(Table P057)
Values for keyboard special codes:
00h (MF2 in codeset2&3 or AT keyboards) keydetection/overrun error
00h (mouse) ID
AAh BAT completion code (sent after errorfree Basic Assurance Test)
ABh first byte of general MF2 keyboard ID
EEh Echo command return
FAh Acknowledge (all general commands except Resend and Echo)
FAh (mouse) Acknowledge (all commands except commands ECh,F2h,FFh)
FCh (MF2) BAT Failure Code (error in second half of the power on self test)
FDh (AT-keyboard) BAT Failure Code (error in the second half of the
power-on self test)
FEh Resend: CPU to controller should resend last keyboard-command
FEh (mouse) CPU to controller should resend last mouse-command
FFh (MF2 in codeset1) keydetection/overrun error
Note: keyboard stops scanning and waits for next command after returning
code FCh or FDh
SeeAlso: PORT 0060h-R
(Table P058)
Values for keyboard typematic rate:
00000b=30.0 10000b=7.5
00001b=26.7 10001b=6.7
00010b=24.0 10010b=6.0
00011b=21.8 10011b=5.5
00100b=20.0 10100b=5.0
00101b=18.5 10101b=4.6
00110b=17.1 10110b=4.3
00111b=16.0 10111b=4.0
01000b=15.0 11000b=3.7
01001b=13.3 11001b=3.3
01010b=12.0 11010b=3.0
01011b=10.9 11011b=2.7
01100b=10.0 11100b=2.5
01101b= 9.2 11101b=2.3
01110b= 8.5 11110b=2.1
01111b= 8.0 11111b=2.0
SeeAlso: #P053
Bitfields for KB controller port B (system control port) [output]:
Bit(s) Description (Table P059)
7 pulse to 1 for IRQ1 reset (PC,XT)
6-4 reserved
3 I/O channel parity check disable
2 RAM parity check disable
1 speaker data enable
0 timer 2 gate to speaker enable
SeeAlso: PORT 0061h-W,#P060
Bitfields for KB controller port B control register (system control port) [input]:
Bit(s) Description (Table P060)
7 RAM parity error occurred
6 I/O channel parity error occurred
5 mirrors timer 2 output condition
4 toggles with each refresh request
3 NMI I/O channel check status
2 NMI parity check status
1 speaker data status
0 timer 2 clock gate to speaker status
SeeAlso: PORT 0061h-R,#P059
Bitfields for Progr. Peripheral Interface (8255) system control port [output]:
Bit(s) Description (Table P061)
7 clear keyboard (only pulse, normally kept at 0)
6 =0 hold keyboard clock low
5 NMI I/O parity check disable
4 NMI RAM parity check disable
3 =0 read low nybble of switches S2
=1 read high nybble of switches S2
2 reserved, often used as turbo switch
original PC: cassette motor off
1 speaker data enable
0 timer 2 gate to speaker enable
Note: bits 2 and 3 are sometimes used as turbo switch
SeeAlso: PORT 0061h-W,#P0051,#P062,#P063,#P064
Bitfields for PPI (XT only) data port C:
Bit(s) Description (Table P062)
7 RAM parity error occurred
6 I/O channel parity error occurred
5 timer 2 channel out
4 reserved
original PC: cassette data input
---
3 system board RAM size type 1
2 system board RAM size type 2
1 coprocessor installed
0 loop in POST
---
3-0 DIL switch S2 high/low nybble (depending on PORT 0061h bit 3)
SeeAlso: PORT 0062h-RW,#P061,#P063,#P064
Bitfields for PPI (PC,XT only) equipment switches [input]:
Bit(s) Description (Table P063)
7-6 number of disk drives
00 1 diskette drive
01 2 diskette drives
10 3 diskette drives
11 4 diskette drives
5-4 initial video
00 reserved (video adapter has on-board BIOS)
01 40*25 color (mono mode)
10 80*25 color (mono mode)
11 MDA 80*25
3-2 memory size (using 256K chips)
00 256K
01 512K
10 576K
11 640K
3-2 memory size (using 64K chips)
00 64K
01 128K
10 192K
11 256K
3-2 memory size (original PC)
00 16K
01 32K
10 48K
11 64K
1-0 reserved
1 NPU (math coprocessor) present
0 boot from floppy
SeeAlso: #P062,#P064,PORT 0060h-R
Bitfields for PPI (8255) command mode register:
Bit(s) Description (Table P064)
7 activation function (0 = bit set/reset, 1 = mode set function)
6,5 port A mode: 00 = mode0, 01 = mode1, 1x = mode2
4 port A direction: 0 = output, 1 = input
3 port C bits 7-4 direction: 0 = output, 1 = input
2 port B mode: 0 = mode0, 1 = mode1
1 port B direction: 0 = output, 1 = input
0 port C bits 3-0 direction: 0 = output, 1 = input
Note: Attention: Never write anything other than 99h to this port
(better: never write anything to this port, only during BIOS
init), as other values may connect multiple output drivers
and will cause hardware damage in PC/XTs! By setting command
word to 99h, PPI will be set in input/output modes as it is
necessary to support the commonly known IO-ports 60, 61, 62
as desired.
SeeAlso: #P061,#P062,#P063
Bitfields for keyboard controller read status (ISA, EISA):
Bit(s) Description (Table P065)
7 parity error on transmission from keyboard
6 receive timeout
5 transmit timeout
4 keyboard interface inhibited by keyboard lock
3 =1 data written to input register is command (PORT 0064h)
=0 data written to input register is data (PORT 0060h)
2 system flag status: 0=power up or reset 1=selftest OK
1 input buffer full (input 60/64 has data for 8042)
no write access allowed until bit clears
0 output buffer full (output 60 has data for system)
bit is cleared after read access
SeeAlso: PORT 0064h-R,#P066,#P067,#P068
Bitfields for keyboard controller read status (MCA):
Bit(s) Description (Table P066)
7 parity error on transmission from keyboard
6 general timeout
5 mouse output buffer full
4 keyboard interface inhibited by keyboard lock
3 =1 data written to input register is command (PORT 0064h)
=0 data written to input register is data (PORT 0060h)
2 system flag status: 0=power up or reset 1=selftest OK
1 input buffer full (60/64 has data for 804x)
no write access allowed until bit clears
0 output buffer full (output 60 has data for system)
bit is cleared after read access
SeeAlso: #P065,#P067,#P068
Bitfields for keyboard controller read status (Compaq):
Bit(s) Description (Table P067)
7 parity error detected (11-bit format only). If an
error is detected, a Resend command is sent to the
keyboard once only, as an attempt to recover.
6 receive timeout. transmission didn't finish in 2mS.
5 transmission timeout error
bit 5,6,7 cause
1 0 0 No clock
1 1 0 Clock OK, no response
1 0 1 Clock OK, parity error
4 =0 security lock engaged
3 =1 data in OUTPUT register is command
=0 data in OUTPUT register is data
2 system flag status: 0=power up or reset 1=soft reset
1 input buffer full (60/64 has data for 804x)
no write access allowed until bit clears
0 output buffer full (port 60 has data for system)
bit is cleared after read access
SeeAlso: #P065,#P066,#P068
(Table P068)
Values for keyboard controller commands (data goes to port 0060)::
Value Description
20h read read byte zero of internal RAM, this is the last KB command
sent to the 8041/8042
Compaq put current command byte on port 0060 (see #P070,#P071)
21-3F read reads the byte specified in the lower 5 bits of the command
in the 804x's internal RAM
60-7F double writes the data byte to the address specified in the 5 lower
bits of the command
60h Compaq Load new command (60 to [64], command to [60]) (see #P071)
(also general AT-class machines)
A0h AMI get ASCIZ copyright message on port 0060
A1h AMI get controller version byte on port 0060
A1h Compaq unknown speedfunction ??
A2h Compaq unknown speedfunction ??
A2h AMI set keyboard controller pins 22 and 23 low
A3h Compaq Enable system speed control
A3h AMI set keyboard controller pins 22 and 23 high
A4h MCA check if password installed
A4h Compaq Toggle speed
A4h AMI set internal system speed flag to low
A5h MCA load password
A5h AMI set internal system speed flag to high
A5h Compaq Special read. the 8042 places the real values of port 2
except for bits 4 and 5 wich are given a new definition in
the output buffer. No output buffer full is generated.
if bit 5 = 0, a 9-bit keyboard is in use
if bit 5 = 1, an 11-bit keyboard is in use
if bit 4 = 0, output-buff-full interrupt disabled
if bit 4 = 1, output-buffer-full interrupt enabled
A6h MCA check password
A6h AMI get internal system speed flag on port 0060
A6h Compaq unknown speedfunction ??
A7h MCA disable mouse port
A7h AMI set internal flag indicating bad write cache
A8h MCA enable mouse port
A8h AMI set internal flag indicating good write cache
A9h MCA test mouse port
A9h AMI get internal flag indicating cache OK to 0060
AAh sngl initiate self-test. will return 55h to data port if self-test
successful, FCh if failed
AAh Compaq initializes ports 1 and 2, disables the keyboard and clears
the buffer pointers. It then places 55h in the output buffer.
ABh sngl initiate interface test. result values:
00h no error
01h keyboard clock line stuck low
02h keyboard clock line stuck high
03h keyboard data line is stuck low
04h keyboard data line stuck high
05h (Compaq only) diagnostic feature
ACh read diagnostic dump. the contents of the 804x RAM, output port,
input port, status word are sent.
ADh sngl disable keyboard (sets bit 4 of commmand byte)
ADh Vectra HP Vectra diagnostic dump
AEh sngl enable keyboard (resets bit 4 of commmand byte)
AFh AWARD Enhanced Command: read keyboard version
B1h AMI set keyboard controller P11 line low
B2h AMI set keyboard controller P12 line low
B3h AMI set keyboard controller P13 line low
B4h AMI set keyboard controller P22 line low
B5h AMI set keyboard controller P23 line low
B8h AMI set keyboard controller P10 line high
B9h AMI set keyboard controller P11 line high
BAh AMI set keyboard controller P12 line high
BBh AMI set keyboard controller P13 line high
BCh AMI set keyboard controller P22 line high
BDh AMI set keyboard controller P23 line high
C0h read read input port and place on PORT 0060h
bit 7 keyboard NOT locked
bit 6 =0 first video is CGA
=1 first video is MDA
bit 5 =0 factory testmode
=1 normal
bit 4 =0 256KB RAM, 1=512KB
bit 5,3-0 are used in Intel chipset 386sx machines with
AMI/Phoenix BIOSes for BIOS specific hardware settings
C0h Compaq places status of input port in output buffer. Use this
command only when the output buffer is empty
C1h MCA Enhanced Command: poll input port Low nibble
C2h MCA Enhanced Command: poll input port High nibble
C8h AMI unblock keyboard controller lines P22 and P23
C9h AMI block keyboard controller lines P22 and P23
CAh AMI read keyboard mode, return in 0060 bit 0
(bit clear if ISA mode, set if PS/2 mode)
CBh AMI set keyboard mode (write back mode byte returned by CAh,
modifying only bit 0)
D0h read read output port and place on PORT 0060h (see #P072)
D0h Compaq places byte in output port in output buffer. Use this command
only when the output buffer is empty
D1h double write output port. The next byte written to port 0060h will
be written to the 804x output port; the original IBM AT and
many compatibles use bit 1 of the output port to control
the A20 gate.
Important: bit 0 (system reset) should always be set here, as
the system may hang constantly, use pulse output port
(FEh) instead.
D1h Compaq the system speed bits are not set by this command use
commands A1-A6 (!) for speed functions.
D2h MCA Enhanced Command: write keyboard output buffer
D3h MCA Enhanced Command: write pointing device out.buf.
D4h MCA write to mouse/pointing device instead of to keyboard; this
controller command must precede every PORT 0060h command
directed to the mouse, otherwise it will be sent to the
keyboard
D4h AWARD Enhanced Command: write to auxiliary device
DDh sngl disable address line A20 (HP Vectra only???)
default in Real Mode
DFh sngl enable address line A20 (HP Vectra only???)
E0h read read test inputs.
bit0 = kbd clock, bit1 = kbd data
Exxx AWARD Enhanced Command: active output port
EDh double this is a two part command to control the state of the
NumLock, CpasLock and ScrollLock LEDs
The second byte contains the state to set LEDs.
bit 7-3 reserved. should be set to 0.
bit 2 = 0 Caps Lock LED off
bit 1 = 0 Num Lock LED off
bit 0 = 0 Scroll Lock LED off
F0-FF sngl pulse output port low for 6 microseconds.
bits 0-3 contain the mask for the bits to be pulsed. A bit is
pulsed if its mask bit is zero
bit0=system reset. Don't set to zero. Pulse only!
Note: keyboard controllers are widely different from each other. You
cannot generally exchange them between different machines.
(Award) Derived from Award's Enhanced KB controller advertising sheet.
(Compaq) Derived from the Compaq Deskpro 386 Tech. Ref. Guide.
(Table P069)
Values for HP Vectra control buffer command code:
00h-54h insert standard key make code into 8041 scancode buf
55h-77h insert HP key make code into 8041 scancode buffer
7Ah pass through next data byte
7Bh set RAM Switch to 0
7Ch set RAM Switch to 1 (default)
7Dh set CRT Switch to 0
7Eh set CRT Switch to 1 (default)
7Fh reserved
80h-D4h insert standard key break code into scancode buffer
D5h-F7h insert HP key break code into scancode buffer
F8h enable AutoPoll
F9h disable AutoPoll
FAh-FEh reserved
FFh keyboard overrun
SeeAlso: PORT 0068h-W
Bitfields for Compaq keyboard command byte:
Bit(s) Description (Table P070)
7 reserved
6 =1 convert KB codes to 8086 scan codes
5 =0 use 11-bit codes, 1=use 8086 codes
4 =0 enable keyboard, 1=disable keyboard
3 ignore security lock state
2 this bit goes into bit2 status reg.
1 reserved (0)
0 generate interrupt when output buffer full
SeeAlso: #P071
Bitfields for keyboard command byte (alternate description):
Bit(s) Description (Table P071)
7 reserved (0)
6 IBM PC compatibility mode
5 IBM PC mode
no parity, no stop bits, no translation
(PS/2) force mouse clock low
4 disable keyboard (clock)
3 inhibit override
(PS/2) reserved
2 system flag
1 reserved (0)
(PS/2) enable mouse output buffer full interrupt
0 enable output buffer full interrupt
SeeAlso: #P070,#P072
Bitfields for keyboard controller output port:
Bit(s) Description (Table P072)
7 keyboard data (output)
6 keyboard clock (output)
5 input buffer empty
4 output buffer empty
3 undefined
2 undefined
used by Intel 386sx Chipset with AMI/Phoenix BIOSes for BIOS-specific
configuration of turbo switch
1 gate address A20
0 system reset
Note: bit 0 (system reset) should always be set when writing the output
port, as the system may hang constantly; use pulse output port
(command FEh) instead.
SeeAlso: #P071
----------P0065------------------------------
PORT 0065 - AT&T 6300+ - HIGH/LOW CHIP SELECT
----------P0065------------------------------
PORT 0065 - ???
0065 RW ???
bit 2: A20 gate control (set = A20 enabled, clear = disabled)
----------P00660067--------------------------
PORT 0066-0067 - AT&T 6300+ - SYSTEM CONFIGURATION SWITCHES
----------P0066------------------------------
PORT 0066 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0069h"Magnetic Stripe"
----------P0068------------------------------
PORT 0068 - C&T CHIPSETS - TURBO MODE CONTROL
----------P0069------------------------------
PORT 0069 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0066h"Magnetic Stripe"
----------P006B006F--------------------------
PORT 006B-006F - SSGA CONTROL REGISTERS
006B ?? RAM enable/remap
006C ?? undocumented
006D ?? undocumented
006E ?? undocumented
006F ?? undocumented
----------P0070007F--------------------------
PORT 0070-007F - CMOS RAM/RTC (REAL TIME CLOCK)
Note: the real-time clock may be either a discrete MC146814, MC146818, or
an emulation thereof built into the motherboard chipset
0070 W CMOS RAM index register port (ISA, EISA)
bit 7 = 1 NMI disabled
= 0 NMI enabled
bit 6-0 CMOS RAM index (64 bytes, sometimes 128 bytes)
any write to 0070 should be followed by an action to 0071
or the RTC wil be left in an unknown state.
0071 RW CMOS RAM data port (ISA, EISA) (see #P073)
(Table P073)
Values for Real-Time Clock register number (see also CMOS.LST):
00h-0Dh clock registers
0Eh diagnostics status byte
0Fh shutdown status byte
10h diskette drive type for A: and B:
11h reserved / IBM fixed disk / setup options
12h fixed disk drive type for drive 0 and drive 1
13h reserved / AMI Extended CMOS setup (AMI Hi-Flex BIOS)
14h equipment byte
15h LSB of system base memory in Kb
16h MSB of system base memory in Kb
17h LSB of total extended memory in Kb
18h MSB of total extended memory in Kb
19h drive C extension byte
1Ah drive D extension byte
1Bh-2Dh reserved
20h-27h commonly used for first user-configurable drive type
2Eh CMOS MSB checksum over 10-2D
2Fh CMOS LSB checksum over 10-2D
30h LSB of extended memory found above 1Mb at POST
31h MSB of extended memory found above 1Mb at POST
32h date century in BCD
33h information flags
34h-3Fh reserved
35h-3Ch commonly used for second user-configurable drive type
3Dh-3Eh word to 82335 MCR memory config register at [22] (Phoenix)
42h-4Ch AMI 1990 Hyundai super-NB368S notebook
???
54h-57h AMI 1990 Hyundai super-NB368S notebook
???
5Ch-5Dh AMI 1990 Hyundai super-NB368S notebook
???
60h-61h AMI 1990 Hyundai super-NB368S notebook
???
----------P0073------------------------------
PORT 0073 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0075h
0073 RW ???
bit 7: ???
bit 6: disable ROM shadowing
bit 5: ??? (related to IDE controller)
bit 4: ???
bit 3: ???
----------P00740076--------------------------
PORT 0074-0076 - SECONDARY CMOS (Compaq), NVRAM (IBM) ACCESS
Note: NVRAM may be 2K, 8K, or 16K
SeeAlso: PORT 0070h-007Fh,CMOS.LST
0074 W secondary CMOS RAM (IBM NVRAM) index, low byte
0075 W secondary CMOS RAM (IBM NVRAM) index, high byte
0076 RW secondary CMOS RAM (IBM NVRAM) data byte
----------P0075------------------------------
PORT 0075 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0073h,PORT 0078h"82378IB"
0075 R? ???
bits 3-2: external bus speed???
00 50 MHz
01 66 MHz
10 60 MHz
11 40 MHz
----------P0078------------------------------
PORT 0078 - HP-Vectra - HARD RESET: NMI ENABLE/DISABLE
0078 ?W NMI enable/disable
bit 7 = 0 disable & clear hard reset from HP-HIL controller
= 1 enable hard reset from HP-HIL controller chip
bit 6-0 reserved
----------P0078------------------------------
PORT 0078 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - BIOS COUNT-DOWN TIMER
Notes: the BIOS uses this port for certain fine timings; presumably it is
independent of processor speed (it appears to decrement at about
300 kHz on my Pentium/90)
the address at which this port appears may be set via the 82378's
PCI configuration space word at offset 0080h (see #0611), or the
timer may be disabled entirely
SeeAlso: PORT 0075h
0078w W set count-down timer
0078w R get current count (timer stops when it reaches 0000h)
----------P0078007F--------------------------
PORT 0078-007F - PC radio by CoZet Info Systems
Range: The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
Note: All of these addresses show a readout of FFh in initial state.
Once started, all of the addresses show FBh, whatever might happen.
----------P007C007D--------------------------
PORT 007C-007D - HP-Vectra - PIC 3 - PROGRAMMABLE INTERRUPT CONTROLLER (8259)
Notes: cascaded to first controller.
used for keyboard and input device interface.
SeeAlso: PORT 0020h-0021h,INT 68"Vectra",INT 6E"Vectra"
007C RW HP-Vectra PIC 3 see at 0020 PIC 1
007D RW HP-Vectra PIC 3 see at 0021 PIC 1
----------P0080------------------------------
PORT 0080 - MANUFACTURING DIAGNOSTICS PORT
Note: sometimes used for a POST hex display
0080 W Manufacturing Diagnostics port
0080 R ???
(Table P074)
Values for AMI BIOS diagnostics codes:
00h system boot completed, control passed to INT 19 bootstrap loader
01h register test
02h video initialization; NMIs disabled
03h power-on delay complete
04h pre-keyboard-test initializations complete
05h soft-reset/power-on setting determined
06h ROM enabled
07h ROM BIOS checksum test passed
08h keyboard BAT command issued
09h keyboard controller BAT result verified
0Ah keyboard controller command code issued
0Bh keyboard controller command byte written
0Ch keyboard controller pins 23/24 blocked and unblocked
0Dh keyboard controller NOP processing in progress
0Eh CMOS RAM shutdown register read/write test passed
0Fh CMOS RAM checksum calculation complete
10h CMOS RAM initialization complete
11h CMOS RAM status register initialized
12h DMA controllers 1/2 and interrupt controllers 1/2 disabled
13h video display disabled, port B initialized
14h chipset initialization, auto memory detection
15h 8254 channel 2 test half complete
16h 8254 channel 2 test completed
17h 8254 channel 1 test completed
18h 8254 channel 0 test completed
19h memory refresh started
1Ah memory refresh line is toggling
1Bh memory refresh test completed
20h base 64K memory test started
21h address line test passed
22h parity toggle complete
23h base 64K sequential read/write test passed
24h pre-interrupt-vector-initialization configuration complete
25h interrupt vectors initialized
26h 8042 input port read
27h global data initialization complete
28h post-interrupt-vector-initialization initialization complete
29h monochrome mode set
2Ah color mode set
2Bh parity toggle on option video ROM test complete
2Ch initialization before video ROM control complete
2Dh video ROM check complete
2Eh !!!
A9h returned from E0000h adapter ROM
AAh final initializations after adapter ROM initializations complete
----------P0080008F--------------------------
PORT 0080-008F - DMA PAGE REGISTERS (74612)
0080 RW extra page register (temporary storage)
0081 RW DMA channel 2 address byte 2
0082 RW DMA channel 3 address byte 2
0083 RW DMA channel 1 address byte 2
0084 RW extra page register
0085 RW extra page register
0086 RW extra page register
0087 RW DMA channel 0 address byte 2
0088 RW extra page register
0089 RW DMA channel 6 address byte 2
008A RW DMA channel 7 address byte 2
008B RW DMA channel 5 address byte 2
008C RW extra page register
008D RW extra page register
008E RW extra page register
008F RW DMA refresh page register
----------P0080009F--------------------------
PORT 0080-009F - Intel386sx CHIPSET 82231
Note: includes the DMA controller functionality on PORT 0080h to PORT 008Fh
----------P0084------------------------------
PORT 0084 - Compaq POST Diagnostic
--------X-P0084------------------------------
PORT 0084 - EISA - SYNCHRONIZE BUS CYCLE
----------P00850086--------------------------
PORT 0085-0086 - Intel "Triton" chipset - ???
SeeAlso: PORT 00EBh"Triton"
0085 ?W ???
0086 ?W ???
----------P0090009F--------------------------
PORT 0090-009F - PS/2 - POS (PROGRAMMABLE OPTION SELECT)
0090 ?? Central arbitration control port
0091 R Card selection feedback
0092 RW PS/2 system control port A (port B is at 0061) (see #P075)
0094 W system board enable/setup register (see #P076)
0095 -- reserved
0096 W adapter enable / setup register
bit 3 = 1 setup adapters
= 0 enable registers
0097 -- reserved
Bitfields for PS/2 system control port A:
Bit(s) Description (Table P075)
7-6 any bit set to 1 turns activity light on
5 reserved
4 watchdog timout occurred
3 =0 RTC/CMOS security lock (on password area) unlocked
=1 CMOS locked (done by POST)
2 reserved
1 A20 is active
0 =0 system reset or write
=1 pulse alternate reset pin (alternate CPU reset)
SeeAlso: #P076
Bitfields for PS/2 system board enable/setup register:
Bit(s) Description (Table P076)
7 =1 enable functions
=0 setup functions
5 =1 enables VGA
=0 setup VGA
2 =1 enable integrated SCSI (PS/2 M77)
=0 setup integrated SCSI
SeeAlso: #P075
----------P00A000AF--------------------------
PORT 00A0-00AF - PIC 2 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 0020h-003Fh"PIC 1",INT 70"IRQ8",INT 77"IRQ15"
00A0 RW NMI mask register (XT)
bit 7 = 0 disabled
= 1 enabled
00A0 RW PIC 2 same as 0020 for PIC 1
00A1 RW PIC 2 same as 0021 for PIC 1 except for OCW1 (see #P077)
Bitfields for PIC2 output control word OCW2:
Bit(s) Description (Table P077)
7 disable IRQ15 (reserved)
6 disable IRQ14 (fixed disk interrupt)
5 disable IRQ13 (coprocessor exception interrupt)
4 disable IRQ12 (mouse interrupt)
3 disable IRQ11 (reserved)
2 disable IRQ10 (reserved)
1 disable IRQ9 (redirect cascade)
0 disable IRQ8 (real-time clock interrupt)
SeeAlso: #P010
----------P00B000BF--------------------------
PORT 00B0-00BF - PC radio by CoZet Info Systems
Range: The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
Notes: All of these addresses show a readout of FFh in initial state.
Once started, all of the addresses show FBh, whatever might happen.
----------P00B2------------------------------
PORT 00B2 - Intel 82420EX chipset - Advanced Power Management Control
Notes: used to pass data between the operating system and the System
Management Interrupt (SMI) handler
writes to this port can cause an SMI; reads can cause STPCLK# to be
asserted (putting the CPU in sleep mode)
SeeAlso: PORT 00B3h
00B2 RW control
----------P00B3------------------------------
PORT 00B3 - Intel 82420EX chipset - Advanced Power Management Status
Note: used to pass data between the operating system and the System
Management Interrupt (SMI) handler
SeeAlso: PORT 00B2h
00B3 RW status
----------P00C0------------------------------
PORT 00C0 - TI SN746496 programmable tone/noise generator (PCjr)
----------P00C000DF--------------------------
PORT 00C0-00DF - DMA 2 - SECOND DIRECT MEMORY ACCESS CONTROLLER (8237)
00C0 RW DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2 RW DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4 RW DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6 RW DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8 RW DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA RW DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC RW DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE RW DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)
00D0 R DMA channel 4-7 status register (ISA, EISA) (see #P078)
00D0 W DMA channel 4-7 command register (ISA, EISA) (see #P079)
00D2 W DMA channel 4-7 write request register (ISA, EISA)
00D4 W DMA channel 4-7 write single mask register (ISA, EISA) (see #P080)
00D6 W DMA channel 4-7 mode register (ISA, EISA) (see #P081)
00D8 W DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)
00DA R DMA channel 4-7 read temporary register (ISA, EISA)
00DA W DMA channel 4-7 master clear (ISA, EISA)
00DC W DMA channel 4-7 clear mask register (ISA, EISA)
00DE W DMA channel 4-7 write mask register (ISA, EISA)
Bitfields for DMA channel 4-7 status register:
Bit(s) Description (Table P078)
7 = 1 channel 7 request
6 = 1 channel 6 request
5 = 1 channel 5 request
4 = 1 channel 4 request
3 = 1 terminal count on channel 7
2 = 1 terminal count on channel 6
1 = 1 terminal count on channel 5
0 = 1 terminal count on channel 4
SeeAlso: #P001,#P079
Bitfields for DMA channel 4-7 command register:
Bit(s) Description (Table P079)
7 DACK sense active high
6 DREQ sense active high
5 =1 extended write selection
=0 late write selection
4 rotating priority instead of fixed priority
3 compressed timing
2 =1 enable controller
=0 enable memory-to-memory transfer
1-0 channel number (00 = 4 to 11 = 7)
SeeAlso: #P002,#P078,#P080
Bitfields for DMA channel 4-7 write single mask register:
Bit(s) Description (Table P080)
7-3 reserved
2 =0 clear mask bit
=1 set mask bit
1-0 channel select
00 channel 4 select
01 channel 5 select
10 channel 6 select
11 channel 7 select
SeeAlso: #P004,#P079
Bitfields for DMA channel 4-7 mode register:
Bit(s) Description (Table P081)
7-6 transfer mode
00 demand mode
01 single mode
10 block mode
11 cascade mode
5 direction
0 address increment select
1 address decrement select
4 autoinitialisation enabled
3-2 operation
00 verify operation
01 write to memory
10 read from memory
11 reserved
1-0 channel number
00 channel 4 select
01 channel 5 select
10 channel 6 select
11 channel 7 select
SeeAlso: #P005,#P080
----------P00E000E1--------------------------
PORT 00E0-00E1 - CHIPSET FROM ACT
00E0 ?W index for accesses to data port
00E1 R? chip set data
----------P00E000E7--------------------------
PORT 00E0-00E7 - MICROCHANNEL
00E0 RW split address register, memory encoding registers PS/2m80 only
00E1 RW memory register
00E3 RW error trace
00E4 RW error trace
00E5 RW error trace
00E7 RW error trace
----------P00E1------------------------------
PORT 00E1 - STB PowerMEG - ???
Desc: the STB PowerMEG is a memory expansion card capable of providing EMS
00E1 RW ???
bit 0: ???
----------P00EB------------------------------
PORT 00EB - Intel "Triton" chipset - ???
SeeAlso: PORT 0085h"Triton"
00EB ?W ???
----------P00EC00ED--------------------------
PORT 00EC-00ED - Compaq LTE Elite
----------P00ED------------------------------
PORT 00ED - ???
Note: on a number of machines, the BIOS appears to write a copy of any
data sent to numerous other ports to this port as well
00EDw ?W ???
----------P00EF------------------------------
PORT 00EF - Hyunday Super-NB386S (AMD386sx with Intel chipset)
Warning: any access to this port causes a cold reset on this machine!
----------P00F000F5--------------------------
PORT 00F0-00F5 - PCjr Disk Controller
00F0 ?? disk controller
00F2 ?? disk controller control port
00F4 ?? disk controller status register
00F5 ?? disk controller data port
----------P00F000FF--------------------------
PORT 00F0-00FF - coprocessor (8087..80387)
00F0 W math coprocessor clear busy latch
00F1 W math coprocessor reset
00F8 RW opcode transfer
00FA RW opcode transfer
00FC RW opcode transfer
----------P00F9------------------------------
PORT 00F9 - Compaq LTE Elite
----------P00FB------------------------------
PORT 00FB - Compaq LTE Elite
----------P00F900FF--------------------------
PORT 00F9-00FF - PC radio by CoZet Info Systems
Range: The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
Notes: All of these addresses show a readout of FFh in initial state.
Once started, all of the addresses show FBh, whatever might happen.
----------P0100------------------------------
PORT 0100 - 3COM 3C509 Ethernet card - ID port
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0110h,PORT 0120h
----------P01000107--------------------------
PORT 0100-0107 - PS/2 POS (Programmable Option Select)
Note: the default value for PORT 0102h is stored in CMOS 31h
0100 R POS register 0 Low adapter ID byte
0101 R POS register 1 High adapter ID byte
0102 RW POS register 2 option select data byte 1 (see #P082)
0103 RW POS register 3 option select data byte 2
0104 RW POS register 4 option select data byte 3
0105 RW POS register 5 option select data byte 4
bit 7 channel active (-CHCK)
bit 6 channel status
0106 RW POS register 6 Low subaddress extension
0107 RW POS register 7 High subaddress extension
Bitfields for PS/2 POS register 2, option select data byte 1:
Bit(s) Description (Table P082)
7 0 = unidirectional LPT port
1 = bidirectional LPT port
6-5 PS/2 Model 50 and higher
00b = default LPT port at 3BCh
01b = "" 378h
10b = "" 278h
11b = reserved
4 reserved
0 card enable (CDEN)
0 =1 VGA sleep bit, disconnects output drivers from VGA (usage for VGA
without monitor)
---ET4000---
7-4 reserved???
3 video RAM wait enable
2 ET4000: ROM BIOS wait enable
1 ET4000: I/O wait enable
Note: access to this port is only possible when PORT 0094h bit 7 is low.
----------P0100010F--------------------------
PORT 0100-010F - CompaQ Tape drive adapter. alternate address at 0300
----------P0108010F--------------------------
PORT 0108-010F - IBM PS/2 - 8 digit LED info panel
010F W leftmost character on display
010E W second character
...
0108 W eighth character
----------P0110------------------------------
PORT 0110 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0120h"3COM"
----------P0120------------------------------
PORT 0120 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0110h"3COM"
----------P0130013F--------------------------
PORT 0130-013F - CompaQ SCSI adapter. alternate address at 0330
----------P01300133--------------------------
PORT 0130-0133 - Adaptec 154xB/154xC SCSI adapter.
Range: alternate address at 0134, 0230, 0234, 0330 and 0334
----------P01340137--------------------------
PORT 0134-0137 - Adaptec 154xB/154xC SCSI adapter.
Range: alternate address at 0130, 0230, 0234, 0330 and 0334
----------P0138013F--------------------------
PORT 0138-013F - PC radio by CoZet Info Systems
Range: The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
Notes: All of these addresses show a readout of FFh in initial state.
Once started, all of the addresses show FBh, whatever might happen.
----------P0140014F--------------------------
PORT 0140-014F - SCSI (alternate Small Computer System Interface) adapter
Note: first adapter is at 0340-034F
----------P01400157--------------------------
PORT 0140-0157 - RTC (alternate Real Time Clock for XT) (1st at 0340-0357)
----------P015C015D--------------------------
PORT 015C-015D - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 026Eh,PORT 0398h
015C W index for data port
015D RW EPP command data
----------P015F------------------------------
PORT 015F - ARTEC Handyscanner A400Z. alternate address at 35F.
----------P0168016F--------------------------
PORT 0168-016F - 4th (Quaternary) EIDE Controller
Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P01700177--------------------------
PORT 0170-0177 - HDC 2 (2nd Fixed Disk Controller) (ISA, EISA)
Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P01780179--------------------------
PORT 0178-0179 - Power Management
0178 W index selection for data port
0179 RW power management data
----------P0178017F--------------------------
PORT 0178-017F - PC radio by CoZet Info Systems
Range: The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
Notes: All of these addresses show a readout of FFh in initial state.
Once started, all of the addresses show FBh, whatever might happen.
----------P01CE01CF--------------------------
PORT 01CE-01CF - ATI Mach32 video chipset - ???
01CE W index register
01CF RW data register
----------P01E801EF--------------------------
PORT 01E8-01EF - Headland HL21 & Acer M5105 chipsets - SYSTEM CONTROL
01ED RW select internal register. Data to/from 01EF
01EE R ???
01EF RW register value
05h = 1000xxxx for low CPU clock speed (4MHz on Morse/Mitac)
= 0xxxxxxx for high CPU clock speed (16MHz on Morse/Mitac)
10h memory size
bits 2-0 = size
(undefined,512K,640K,1024K,2560K,2048K,4096K,undef.)
14h ???
bit 2: 384K RAM of first 1024K relocated to top of memory
----------P01E801EF--------------------------
PORT 01E8-01EF - 3rd (Tertiary) EIDE Controller
Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 0170h-0177h,PORT 01F0h-01F7h
----------P01F001F7--------------------------
PORT 01F0-01F7 - HDC 1 (1st Fixed Disk Controller) (ISA, EISA)
Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h
01F0 RW data register
01F1 R error register (see #P083)
01F1 W WPC/4 (Write Precompensation Cylinder divided by 4)
01F2 RW sector count
01F3 RW sector number (CHS mode)
logical block address, bits 0-7 (LBA mode)
01F4 RW cylinder low (CHS mode)
logical block address, bits 15-8 (LBA mode)
01F5 RW cylinder high (CHS mode)
logical block address, bits 23-16 (LBA mode)
01F6 RW drive/head (see #P084)
01F7 R status register (see #P085)
01F7 W command register (see #P086)
Bitfields for Hard Disk Controller error register:
Bit(s) Description (Table P083)
---diagnostic mode errors---
7 which drive failed (0 = master, 1 = slave)
6-3 reserved
2-0 error code
001 no error detected
010 formatter device error
011 sector buffer error
100 ECC circuitry error
101 controlling microprocessor error
---operation mode---
7 bad block detected
6 uncorrectable ECC error
5 reserved
4 ID found
3 reserved
2 command aborted prematurely
1 track 000 not found
0 DAM not found (always 0 for CP-3022)
SeeAlso: #P084,#P085
Bitfields for hard disk controller drive/head specifier:
Bit(s) Description (Table P084)
7 =1
6 LBA mode enabled, rather than default CHS mode
5 =1
4 drive select (0 = drive 0, 1 = drive 1)
3-0 head select bits (CHS mode)
logical block address, bits 27-24 (LBA mode)
SeeAlso: #P083,#P085
Bitfields for hard disk controller status register:
Bit(s) Description (Table P085)
7 controller is executing a command
6 drive is ready
5 write fault
4 seek complete
3 sector buffer requires servicing
2 disk data read successfully corrected
1 index - set to 1 each disk revolution
0 previous command ended in an error
SeeAlso: #P083,#P086
(Table P086)
Values for hard disk controller command codes:
Command Spec Type Proto Description class:
00h opt nondata NOP
1xh opt nondata recalibrate 1
20h req PIOin read sectors with retry 1
21h req PIOin read sectors without retry 1
22h req PIOin read long with retry 1
23h req PIOin read long without retry 1
30h req PIOout write sectors with retry 2
31h req PIOout write sectors without retry 2
32h req PIOout write long with retry 2
33h req PIOout write long without retry 2
3Ch IDE opt PIOout write verify 3
40h req nondata read verify sectors with retry 1
41h req nondata read verify sectors without retry 1
50h req vend format track 2
7xh req nondata seek 1
8xh IDE vendor vend vendor unique 3
90h req nondata execute drive diagnostics 1
91h req nondata initialize drive parameters 1
92h opt PIOout download microcode
94h E0h IDE opt nondata standby immediate 1
95h E1h IDE opt nondata idle immediate 1
96h E2h IDE opt nondata standby 1
97h E3h IDE opt nondata idle 1
98h E5h IDE opt nondata check power mode 1
99h E6h IDE opt nondata set sleep mode 1
9Ah IDE vendor vend vendor unique 1
C0h-C3h IDE vendor vend vendor unique 2
C4h IDE opt PIOin read multiple 1
C5h IDE opt PIOout write multiple 3
C6h IDE opt nondata set multiple mode 1
C8h IDE opt DMA read DMA with retry 1
C9h IDE opt DMA read DMA without retry 1
CAh IDE opt DMA write DMA with retry 3
CBh IDE opt DMA write DMA w/out retry 3
DBh ATA-2 opt vend acknowledge media chng [Removable]
DCh ATA-2 opt vend Boot / Post-Boot [Removable]
DDh ATA-2 opt vend Boot / Pre-Boot (ATA-2) [Removable]
DEh ATA-2 opt vend door lock [Removable]
DFh ATA-2 opt vend door unlock [Removable]
E0h-E3h (see 94h-96h)
E4h IDE opt PIOin read buffer 1
E5h-E6h (see 98h-99h)
E8h IDE opt PIOout write buffer 2
E9h IDE opt PIOout write same 3
EAh ATA-3 opt Secure Disable [Security Mode]
EAh ATA-3 opt Secure Lock [Security Mode]
EAh ATA-3 opt Secure State [Security Mode]
EAh ATA-3 opt Secure Enable WriteProt [Security Mode]
EBh ATA-3 opt Secure Enable [Security Mode]
EBh ATA-3 opt Secure Unlock [Security Mode]
ECh IDE req PIOin identify drive 1 (see #P087)
EDh ATA-2 opt nondata media eject [Removable]
EEh ATA-3 opt identify device DMA (see #P087)
EFh IDE opt nondata set features 1
F0h-F4h IDE vend EATA standard
F5h-FFh IDE vendor vend vendor unique 4
SeeAlso: #P083,#P085
Format of IDE Identify Drive information:
Offset Size Description (Table P087)
00h WORD general configuration
02h WORD number of logical cylinders
04h WORD reserved
06h WORD number of logical heads
08h WORD vendor-specific
0Ah WORD vendor-specific
0Ch WORD number of logical sectors
0Eh WORD vendor-specific
10h WORD vendor-specific
12h WORD vendor-specific
14h 10 WORDs serial number
no serial number if first word is 0000h
else blank-padded ASCII serial number
28h WORD vendor-specific
[controller type]
2Ah WORD vendor-specific
[controller buffer size in 512-byte sectors]
2Ch WORD number of vendor-specific (usually ECC) bytes on
Read/Write Long
2Eh 4 WORDs firmware revision
no revision number if first word is 0000h
else blank-padded ASCII revision number
36h 20 WORDs model number
no model number if first word is 0000h
else blank-padded ASCII model string
5Eh WORD read/write multiple support
bits 7-0: maximum number of sectors per block supported
00h if read/write multiple not supported
60h WORD reserved (0)
able to do doubleword transfers if nonzero ???
62h WORD capabilities (see #P088)
64h WORD security mode
bit 15: security-mode feature set supported
bits 14-8: maximum number of passwords supported
66h WORD PIO data transfer cycle timing
68h WORD single-word DMA data transfer cycle timing
6Ah WORD field validity
bit 0: offsets 6Ch-73h valid
bit 1: offsets 80h-8Dh valid
6Ch WORD logical cylinders in current translation mode
6Eh WORD logical heads in current translation mode
70h WORD logical sectors per track in current translation mode
72h 2 WORDs current capacity in sectors (excluding device-specific uses)
76h WORD multiple-sector count for read/write multiple command
78h 2 WORDs total number of user-addressable sectors (LBA mode)
00000000h if LBA mode not supported
7Ch WORD single-word DMA transfer modes
low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
7Eh WORD multiword DMA transfer
low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
80h WORD supported flow control PIO transfer modes
82h WORD minimum multiword DMA transfer cycle time
84h WORD recommended multiword DMA cycle time
86h WORD minimum non-flow-control PIO transfer cycle time
88h WORD minimum PIO transfer cycle time with IORDY
8Ah 2 WORDs reserved for future PIO modes (0)
8Eh 58 WORDs reserved (0)
100h 32 WORDs vendor-specific
140h 96 WORDs reserved (0)
Bitfields for IDE capabilities:
Bit(s) Description (Table P088)
13 Standby Timer values used according to ATA standard
11 IORDY supported
10 device can disable use of IORDY
9 LBA mode supported
8 DMA supported
SeeAlso: #P087
----------P01F8------------------------------
PORT 01F8 - ???
01F8 RW ???
bit 0: A20 gate control (set = A20 enabled, clear = disabled)
----------P01F901FF--------------------------
PORT 01F9-01FF - PC radio by CoZet Info Systems
Range: The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
Notes: All of these addresses show a readout of FFh in initial state.
Once started, all of the addresses show FBh, whatever might happen.
--------d-P0200------------------------------
PORT 0200 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0300h"Digidesign"
----------P0200020F--------------------------
PORT 0200-020F - Game port reserved I/O address space
0200-0207 - Game port, eight identical addresses on some boards
0201 R read joystick position and status (see #P089)
0201 W fire joystick's four one-shots
0201 RW gameport on mc-soundmachine, mc 03-04/1992: Adlib-compatible,
Covox 'voice master' & 'speech thing' compatible soundcard.
(enabled if bit1=1 in PORT 038Fh. Because it is disabled on
power-on, it cannot be found by BIOS) (see PORT 0388h-038Fh)
Bitfields for joystick position and status:
Bit(s) Description (Table P089)
7 status B joystick button 2 / D paddle button
6 status B joystick button 1 / C paddle button
5 status A joystick button 2 / B paddle button
4 status A joystick button 1 / A paddle button
3 B joystick Y coordinate / D paddle coordinate
2 B joystick X coordinate / C paddle coordinate
1 A joystick Y coordinate / B paddle coordinate
0 A joystick X coordinate / A paddle coordinate
----------P020002FF--------------------------
PORT 0200-02FF - Sunshine uPW48, programmer for EPROM version CPU's 8748/8749
Range: 4 bit DIP switch installable in the range 20x-2Fx
0200-0203 adresses of the 8255 on the uPW48
0208-020B adresses of ??? on the uPW48 (all showing zeros)
----------P02080209--------------------------
PORT 0208-0209 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, 02E8
----------P020C020F--------------------------
PORT 020C-020F - AIMS LAB PC Radio
Range: configurable to 020C or 030C
----------P02100217--------------------------
PORT 0210-0217 - Expansion unit (XT)
0210 W latch expansion bus data
0210 R verify expansion bus data
0211 W clear wait, test latch
0211 R High byte data address
0212 R Low byte data address
0213 W 0=enable, 1=disable expansion unit
0214 W latch data (receiver card port)
0214 R read data (receiver card port)
0215 R High byte of address, then Low byte (receiver card port)
----------P02100211--------------------------
PORT 0210-0211 - Game Blaster
Range: PORT 02x0h-02x1h, x=1,2,...
0210 W register index
0211 ?W register data
----------P02180219--------------------------
PORT 0218-0219 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02200223--------------------------
PORT 0220-0223 ---- Sound Blaster / Adlib port (Stereo)
SeeAlso: PORT 0388h-0389h
0220 R Left speaker -- Status port
0220 W Left speaker -- Address port
0221 W Left speaker -- Data port
0222 R Right speaker -- Status port
0222 W Right speaker -- Address port
0223 W Right speaker -- Data port
----------P02200227--------------------------
PORT 0220-0227 - Soundblaster PRO and SSB 16 ASP
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 2.0
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 4.0
Note: the FM music is accessible on 0388/0389 for compatibility.
0220 R left FM status port
0220 W left FM music register address port (index)
0221 RW left FM music data port
0222 R right FM status port
0222 W right FM music register address port (index)
0223 RW right FM music data port
0224 W mixer register address port (index)
0225 RW mixer data port
0226 W DSP reset
0228 R FM music status port
0228 W FM music register address port (index)
0229 W FM music data port
022A R DSP read data (voice I/O and Midi)
022C W DSP write data / write command
022C R DSP write buffer status (bit 7)
022E R DSP data available status (bit 7)
----------P022B------------------------------
PORT 022B - GI1904 Scanner Interface Adapter
Range: PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range: PORT 03ABh, PORT 03EBh
----------P022F------------------------------
PORT 022F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note: An Adlib-compatible Covox 'voice master' & 'speech thing' compatible
soundcard
SeeAlso: PORT 0378h"Covox",PORT 0388h-038Fh"soundmachine"
022F RW Covox compatible speech I/O (via internal A/D converter,
each read access starts a new conversion cycle)
register enabled if bit7=1 in PORT 038Fh
----------P02300233--------------------------
PORT 0230-0233 - Adaptec 154xB/154xC SCSI adapter.
alternate address at 0130, 0134, 0230, 0330 and 0334
----------P02340237--------------------------
PORT 0234-0237 - Adaptec 154xB/154xC SCSI adapter.
alternate address at 0130, 0134, 0230, 0330 and 0334
----------P0238023F--------------------------
PORT 0238-023F - COM port addresses on UniRAM card by German magazine c't
selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8
----------P0238023x--------------------------
PORT 0238-023x - Bus Mouse Port (secondary address)
Note: secondary address for bus mice from MS and Logitech, and the ATI
video adapter mouse
----------P023C023x--------------------------
PORT 023C-023x - Bus Mouse Port (primary address)
Note: primary address for bus mice from MS and Logitech, the ATI video
adapter mouse, and the Commodore PC30III bus mouse
----------P0240024F--------------------------
PORT 0240-024F - Gravis Ultra Sound by Advanced Gravis
Range: The I/O address range is dipswitch selectable from:
0200-020F and 0300-030F
0210-021F and 0310-031F
0220-022F and 0320-032F
0230-023F and 0330-033F
0240-024F and 0340-034F
0250-025F and 0350-035F
0260-026F and 0360-036F
0270-027F and 0370-037F
SeeAlso: PORT 0340h-034Fh,PORT 0746h
0240 W Mix Control register (see #P090)
0241 R Read Data
0241 W Trigger Timer
0246 R IRQ Status Register (see #P091)
0248 RW Timer Control Reg
Same as ADLIB Board (see PORT 0200h)
0249 W Timer Data (see #P092)
024B W IRQ Control Register (0240 bit 6 = 1) (see #P093)
024B W DMA Control Register (0240 bit 6 = 0) (see #P094)
024F RW Register Controls (rev 3.4+)
Bitfields for Gravis Ultra Sound mix control register:
Bit(s) Description (Table P090)
6 Control Register Select (see 024B)
5 Enable MIDI Loopback
4 Combine GF1 IRQ with MIDI IRQ
3 Enable Latches
2 Enable MIC IN
1 Disable LINE OUT
0 Disable LINE IN
SeeAlso: #P091
Bitfields for Gravis Ultra Sound IRQ status register:
Bit(s) Description (Table P091)
7 DMA TC IRQ
6 Volume Ramp IRQ
5 WaveTable IRQ
3 Timer 2 IRQ
2 Timer 1 IRQ
1 MIDI Receive IRQ
0 MIDI Transmit IRQ
SeeAlso: #P090,#P093,#P094
Bitfields for Gravis Ultra Sound timer data:
Bit(s) Description (Table P092)
7 Reset Timr IRQ
6 Mask Timer 1
5 Mask Timer 2
1 Timer 2 Start
0 Timer 1 Start
SeeAlso: #P091,#P093
Bitfields for Gravis Ultra Sound IRQ control register:
Bit(s) Description (Table P093)
6 Combine Both IRQ
5-3 MIDI IRQ Selector
000 No IRQ
001 IRQ 2
010 IRQ 5
011 IRQ 3
100 IRQ 7
101 IRQ 11
110 IRQ 12
111 IRQ 15
2-0 GF1 IRQ Selector
000 No IRQ
001 IRQ 2
010 IRQ 5
011 IRQ 3
100 IRQ 7
101 IRQ 11
110 IRQ 12
111 IRQ 15
SeeAlso: #P091,#P094
Bitfields for Gravis Ultra Sound DMA Control Register:
Bit(s) Description (Table P094)
6 Combine Both DMA
5-3 DMA Select Register 2
000 No DMA
001 DMA 1
010 DMA 3
011 DMA 5
100 DMA 6
101 DMA 7
2-0 DMA Select Register 1
000 No DMA
001 DMA 1
010 DMA 3
011 DMA 5
100 DMA 6
101 DMA 7
SeeAlso: #P091,#P093,#P098
----------P02400257--------------------------
PORT 0240-0257 - RTC (alternate Real Time Clock for XT) (1st at 0340-0357)
(used by TIMER.COM v1.2 which is the 'standard' timer program)
----------P02580259--------------------------
PORT 0258-0259 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02580259--------------------------
PORT 0258-0259 ---- AT RAMBANK Memory Expansion Board - EXT. MEMORY AND EMS-SUPPORT
Range: base address may be set to 0218h, 0228h, 0238h, 0258h, 0268h, 0298h,
or 02A8h
----------P0258025F--------------------------
PORT 0258-025F - Intel Above Board
----------P02600268--------------------------
PORT 0260-0268 - LPT port address on the UniRAM card by German magazine c't
selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02680269--------------------------
PORT 0268-0269 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P026B------------------------------
PORT 026B - GI1904 Scanner Interface Adapter
Range: PORT 022Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range: PORT 03ABh, PORT 03EBh
----------P026E026F--------------------------
PORT 026E-026F - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 0398h
026E W index for data port
026F RW EPP command data
----------P0278------------------------------
PORT 0278 - Covox 'Speech Thing' COMPATIBLES
SeeAlso: PORT 022Fh"Covox",PORT 0388h-038Fh"soundmachine"
0278 W speech data output via printer data port
(with mc-soundmachine, enabled if bit5=1 in 38F)
----------P0278027E--------------------------
PORT 0278-027E - parallel printer port, same as 0378 and 03BC
0278 W data port
0279 Rw status port
027A RW control port
----------P0279------------------------------
PORT 0279 - Plug-and-Play - CONFIGURATION REGISTER
SeeAlso: PORT 0A79h
0279 -W index into Plug-and-Play register set for Read Data Port and
Write Data Port I/O (see #P095,#P096)
(Table P095)
Values for Plug-and-Play Card-Level Registers:
00h set Read Port address
bits 9-2 of Read Data port address (bits 15-10 are always 0, bits 1-0
are always 11); valid Read Port addresses are 0203h-03FFh
01h serial isolation
02h configuration control
03h Wake command
(specifies which card is accessed through configuration registers)
04h resource data
05h status
06h Card Select Number (CSN)
07h logical device number
(selects which logical device on card is accessed at locations 30h-FFh)
(see #P096)
08h-1Fh reserved
20h-2Fh vendor-specific
Note: there is one set of these registers per installed card
SeeAlso: #P096
(Table P096)
Values for Plug-and-Play Logical Device Registers:
30h activate
bit 0: device is active on ISA bus
bits 7-1: reserved (0)
31h I/O range check
bit 0: I/O Read Pattern select (if bit 1 set, then I/O reads return
55h if this bit is set, AAh if this bit is clear)
bit 1: I/O Range Check Enable: if set, all reads from device I/O
registers return 55h or AAh, depending on bit 0
bits 7-2: reserved (0)
32h-37h reserved
38h-3Fh vendor-specific
40h-44h 24-bit ISA memory descriptor 0
45h-47h reserved
48h-4Ch 24-bit ISA memory descriptor 1
4Dh-4Fh reserved
50h-54h 24-bit ISA memory descriptor 2
55h-57h reserved
58h-5Ch 24-bit ISA memory descriptor 3
5Dh-5Fh reserved
60h-6Fh I/O configuration registers 0-7
70h-71h IRQ channel select 0
72h-73h IRQ channel select 1
74h-75h DMA configuration registers 0-1
76h-7Eh 32-bit memory range configuration register 0
7Fh reserved
80h-88h 32-bit memory range configuration register 1
89h-8Fh reserved
90h-98h 32-bit memory range configuration register 2
99h-9Fh reserved
A0h-A8h 32-bit memory range configuration register 3
A9h-EFh reserved for logical device configuration
F0h-FEh vendor-specific
FFh reserved
Note: there is one set of these registers per logical device
SeeAlso: #P095
----------P0280------------------------------
PORT 0280 - LCD display on Wyse 2108 PC
----------P02800288--------------------------
PORT 0280-0288 - non-standard COM port addresses (V20-XT by German magazine c't)
selectable from 0280, 0288, 0290, 0298, 6A0, 6A8
----------P0288028F--------------------------
PORT 0288-028F - non-standard COM port addresses (V20-XT by German magazine c't)
0280-0288 selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
0290-0298
0298-029F
----------P02A002A7--------------------------
PORT 02A0-02A7 - Sunshine EW-901BN, EW-904BN
EPROM writer card (release 1986) for EPROMs up to 27512
02A0-02A3 adresses of the 8255 on the EW-90xBN
----------P02A202A3--------------------------
PORT 02A2-02A3 - MSM58321RS clock
----------P02A802A9--------------------------
PORT 02A8-02A9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02AB------------------------------
PORT 02AB - GI1904 Scanner Interface Adapter (default)
Range: PORT 022Bh, PORT 026Bh, PORT 02EBh, PORT 032Bh, PORT 036Bh
Range: PORT 03ABh, PORT 03EBh
Note: the GI1904 is used by many SPI 400/800dpi gray/halftone/color handy
scanners by Marstek, Mustek, Conrad, V”lkner and others
----------P02B002BF--------------------------
PORT 02B0-02BF - Trantor SCSI adapter
----------P02B002DF--------------------------
PORT 02B0-02DF - alternate EGA, primary EGA at 03C0
----------P02B802B9--------------------------
PORT 02B8-02B9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02C002Cx--------------------------
PORT 02C0-02Cx - AST-clock
----------P02C002DF--------------------------
PORT 02C0-02DF - XT-Real Time Clock 2 (default jumpered address)
----------P02E002E8--------------------------
PORT 02E0-02E8 - LPT port address on the UniRAM card by German magazine c't
Range: base address selectable from 0260, 02E0, 02E8, 02F0, 03E0, and 03E8.
----------P02E002EF--------------------------
PORT 02E0-02EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)
(GAB 0 on XT)
02E1 ?? GPIB (adapter 0)
02E2
02E3
----------P02E002EF--------------------------
PORT 02E0-02EF - data aquisition (AT)
02E2 ?? data aquisition (adapter 0)
02E3 ?? data aquisition (adapter 0)
----------P02E8------------------------------
PORT 02E8 - S3 86C928 video controller (ELSA Winner 1000)
----------P02E802E9--------------------------
PORT 02E8-02E9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02E802EF--------------------------
PORT 02E8-02EF - serial port, same as 02F8, 03E8 and 03F8 (COM4)
----------P02E802EF--------------------------
PORT 02E8-02EF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)
02E8 R display status
02E8 W horizontal total
02EA RW Lookup: DAC mask
02EB W Lookup: DAC read index
02EC W Lookup: DAC write index
02ED RW Lookup: DAC data
----------P02EA------------------------------
PORT 02EA - S3 86C928 video controller (ELSA Winner 1000)
----------P02EB------------------------------
PORT 02EB - GI1904 Scanner Interface Adapter
Range: PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 032Bh, PORT 036Bh
Range: PORT 03ABh, PORT 03EBh
----------P02F02F8 --------------------------
PORT 02F0-2F8 - LPT port address on the UniRAM card by German magazine c't
selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02F802FF--------------------------
PORT 02F8-02FF - serial port, same as 02E8, 03E8 and 03F8 (COM2)
02F8 W transmitter holding register
02F8 R receiver buffer register
02F8 RW divisor latch, low byte when DLAB=1
02F9 RW divisor latch, high byte when DLAB=1
02F9 RW interrupt enable register when DLAB=0
02FA R interrupt identification register
02FB RW line control register
02FC RW modem control register
02FD R line status register
02FF RW scratch register
----------P0300------------------------------
PORT 0300 - Award POST Diagnostic
--------d-P0300------------------------------
PORT 0300 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0200h"Digidesign"
----------P03000301--------------------------
PORT 0300-0301 - Soundblaster 16 ASP MPU-Midi
----------P0300????--------------------------
PORT 0300-???? - HP IEC/HP-IB adapter (e.g. for use with tape streamer HP9142)
----------P0300031F--------------------------
PORT 0300-031F - 3com Ethernet adapters (default address)
----------P0300????--------------------------
PORT 0300-???? - NE2000 compatible Ethernet adapters
Range: may be placed at 0300h, 0320h, 0340h, or 0360h
----------P03000303--------------------------
PORT 0300-0303 - Panasonic 52x CD-ROM SCSI Miniport
Range: PORT 0300h-0303h,PORT 0320h-0323h,PORT 0340h-0343h,PORT 0360h-0363h,
and PORT 0380h-0383h
----------P0300030F--------------------------
PORT 0300-030F - Philips CD-ROM player CM50
----------P0300030F--------------------------
PORT 0300-030F - CompaQ Tape drive adapter. alternate address at 0100
----------P0300031F--------------------------
PORT 0300-031F - prototype cards
Periscope hardware debugger
----------P030C030F--------------------------
PORT 030C-030F - AIMS LAB PC Radio
configurable to 020C or 030C
----------P0310031F--------------------------
PORT 0310-031F - Philips CD-ROM player CM50
----------P03200323--------------------------
PORT 0320-0323 - XT HDC 1 (Hard Disk Controller)
SeeAlso: PORT 01F0h-01F7h
0320 RW data register
0321 W reset controller
0321 R read controller hardware status (see #P097)
0322 R read DIPswitch setting on XT controller card
0322 W generate controller-select pulse
0323 W write pattern to DMA and INT mask register
Bitfields for XT hard disk controller hardware status:
Bit(s) Description (Table P097)
7-6 always 0
5 logical unit number
4-2 always 0
1 error occurred
0 always 0
----------P03240327--------------------------
PORT 0324-0327 - XT HDC 2 (Hard Disk Controller)
----------P0328032B--------------------------
PORT 0328-032B - XT HDC 3 (Hard Disk Controller)
----------P032B------------------------------
PORT 032B - GI1904 Scanner Interface Adapter
Range: PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 036Bh
Range: PORT 03ABh, PORT 03EBh
----------P032C032F--------------------------
PORT 032C-032F - XT HDC 4 (Hard Disk Controller)
----------P03300331--------------------------
PORT 0330-0331 - MIDI interface
----------P03300333--------------------------
PORT 0330-0333 - Adaptec 154xB/154xC SCSI adapter. default address.
Range: alternate address at 0130, 0134, 0230, 0234 and 0334
----------P0330033F--------------------------
PORT 0330-033F - CompaQ SCSI adapter. alternate address at 0130
----------P0330033F--------------------------
PORT 0330-033F - Philips CD-ROM player CM50
----------P03340337--------------------------
PORT 0334-0337 - Adaptec 154xB/154xC SCSI adapter.
Range: alternate address at 0130, 0134, 0230, 0234 and 0330
----------P0338------------------------------
PORT 0338 - AdLib soundblaster card
----------P0338033F--------------------------
PORT 0338-033F - COM port addresses on UniRAM card by German magazine c't
Range: selectable from 0238, 02E8, 02F8, 0338, 03E0, 03E8, 03F8
----------P0340034F--------------------------
PORT 0340-034F - Philips CD-ROM player CM50
----------P0340034F--------------------------
PORT 0340-034F - SCSI (1st Small Computer System Interface) adapter
Note: alternate address at 0140-014F
----------P0340034F--------------------------
PORT 0340-034F - Gravis Ultra Sound by Advanced Gravis
Range: The I/O address range is dipswitch selectable from:
0200-020F and 0300-030F
0210-021F and 0310-031F
0220-022F and 0320-032F
0230-023F and 0330-033F
0240-024F and 0340-034F
0250-025F and 0350-035F
0260-026F and 0360-036F
0270-027F and 0370-037F
SeeAlso: PORT 0240h-024Fh,PORT 0746h
0340 W MIDI Control (see #P098)
0340 R MIDI Status (see #P099)
0341 W MIDI Transmit Data
0341 R MIDI Receive Data
0342 RW GF1 Page Register / Voice Select
0343 RW GF1/Global Register Select (see #P100)
0344 RW GF1/Global Data Low Byte (16 bits)
0345 RW GF1/Global Data High Byte (8 bits)
0346 W Mixer Data Port
0347 RW GF1 DRAM
Direct Read Write at Loction pointed with regs 43 and 44
Bitfields for Gravis Ultra Sound MIDI control register:
Bit(s) Description (Table P098)
7 Receive IRQ (1 = enabled)
5-6 Xmit IRQ
0-1 Master Reset (1 = enabled)
SeeAlso: #P091,#P093,#P099
Bitfields for Gravis Ultra Sound MIDI status register:
Bit(s) Description (Table P099)
7 Interrupt pending
5 Overrun Error
4 Framing Error
1 Transmit Register Empty
0 Receive Register Empty
SeeAlso: #P098,#P100
(Table P100)
Values for Gravis Ultra Sound GF1/Global Registers:
---Voice specific registers---
00h w Voice Control (see #P101)
01h w Frequency Control
bit 15-10 Integer Portion
bit 9-1 Fractional Portion
02h w Start Address HIGH
bit 12-0 Address Lines 19-7
03h w Start Address LOW
bit 15-9 Address Lines 6-0
bit 8-5 Fractional Part of Start Address
04h w End Address HIGH
bit 12-0 Address Lines 19-7
05h w End Address LOW
bit 15-9 Address Lines 6-0
bit 8-5 Fractional Part of End Address
06h w Volume Ramp Rate
bit 5-0 Amount added
bit 7-6 Rate
07h w Volume Ramp Start
bit 7-4 Exponent
bit 3-0 Mantissa
08h w Volume Ramp End
bit 7-4 Exponent
bit 3-0 Mantissa
09h w Current Volume
bit 15-12 Exponent
bit 11-4 Mantissa
0Ah w Current Address HIGH
bit 12-0 Address Lines 19-7
0Bh w Current Address LOW
bit 15-9 Address Lines 6-0
bit 8-0 Fractional Position
0Ch w Pan Position
bit 3-0 Pan Postion
0Dh w Volume Control (see #P102)
0Eh w Active Voices
bit 5-0 #Voices -1 (allowed 13 - 31)
0Fh w IRQ Source Register (see #P103)
---NOT voice specific---
41h r/w DRAM DMA Control (see #P104)
42h w DMA Start Address
bits 15-0 DMA Address Lines 19-4
43h w DRAM I/O Address LOW
44h w DRAM I/O Address HIGH
bits 0-3 Upper 4 Address Lines
45h r/w Timer Control
bit 3 Enable Timer 2
bit 2 Enable Timer 1
46h w Timer 1 Count (granularity of 80 micro sec)
47h w Timer 2 Count (granulatity of 320 micro sec)
48h w Sampling Frequency
rate = 9878400 / (16 * (FREQ + 2))
49h r/w Sampling Control (see #P105)
4Bh w Joystick Trim DAC
4Ch r/w RESET
bit 2 GF1 Master IRQ Enable
bit 1 DAC Enable
bit 0 Master Reset
---Voice specific registers---
80h r Voice Control (see 00h)
81h r Frequency Control (see 01h)
82h r Start Address HIGH (see 02h)
83h r Start Address LOW (see 03h)
84h r End Address HIGH (see 04h)
85h r End Address LOW (see 05h)
86h r Volume Ramp Rate (see 06h)
87h r Volume Ramp Start (see 07h)
88h r Volume Ramp End (see 08h)
89h r Current Volume (see 09h)
8Ah r Current Address HIGH (see 0Ah)
8Bh r Current Address LOW (see 0Bh)
8Ch r Pan Position (see 0Ch)
8Dh r Volume Control (see 0Dh)
8Eh r Active Voices (see 0Eh)
8Fh r IRQ Status (see 0Fh)
SeeAlso: #P099
Bitfields for Gravis Ultra Sound voice control global register:
Bit(s) Description (Table P101)
7 IRQ pending
6 Direction
5 Enable WAVE IRQ
4 Enable bi-directional Looping
3 Enable Looping
2 Size data (8/16 bits)
1 Stop Voice
0 Voice Stopped
SeeAlso: #P100,#P102
Bitfields for Gravis Ultra Sound volume control global register:
Bit(s) Description (Table P102)
7 IRQ Pending
6 Direction
5 Enable Volume Ramp IRQ
4 Enable bi-directional Looping
3 Enable Looping
2 Rollover Condition
1 Stop Ramp
0 Ramp Stopped
SeeAlso: #P100,#P101
Bitfields for Gravis Ultra Sound IRQ source register:
Bit(s) Description (Table P103)
7 WaveTable IRQ pending
6 Volume Ramp IRQ pending
4-0 Voice Number
SeeAlso: #P100,#P101,#P104
Bitfields for Gravis Ultra Sound DRAM DMA control register:
Bit(s) Description (Table P104)
7 Invert MSB
6 Data Size (8/16 bits)
5 DMA Pending
3-4 DMA Rate Divider
2 DMA Channel Width (8/16 bits)
1 DMA Direction (1 = read)
0 DMA Enable
SeeAlso: #P100,#P103
Bitfields for Gravis Ultra Sound sampling control register:
Bit(s) Description (Table P105)
7 Invert MSB
6 DMA IRQ pending
5 DMA IRQ enable
2 DMA width (8/16 bits)
1 Mode (mone/stereo)
0 Start Sampling
SeeAlso: #P100
----------P03400357--------------------------
PORT 0340-0357 - RTC (1st Real Time Clock for XT)
(used by TIMER.COM v1.2 which is the 'standard' timer program)
Range: alternate at 0240-0257
SeeAlso: PORT 0240h-0257h
0340 RW 0.001 seconds 0-99
0341 RW 0.1 and 0.01 seconds 0-99
0342 RW seconds 0-59
0343 RW minutes 0-59
0343 RW hours 0-23
0345 RW day of week 1-7
0346 RW day of month 1-31
0347 RW month 1-12
0348 RW RAM (upper nybble only)
0349 RW year 0-99
034A RW RAM last month storage
034B RW RAM year storage (-80)
034C RW RAM reserved
034D RW RAM not used
034E RW RAM not used
034F RW RAM not used
0350 R interrupt status register
0351 W interrupt control register
0352 W counter reset
0353 W RAM reset
0354 R status bit
0355 W GO command
0356 ?? standby interrupt
0357 ?? test mode
----------P03480357--------------------------
PORT 0348-0357 - DCA 3278
----------P034C034F--------------------------
PORT 034C-034F - Gravis UltraMax by Advanced Gravis
Range: The I/O address range is dipswitch selectable from:
0200-020F and 0300-030F
0210-021F and 0310-031F
0220-022F and 0320-032F
0230-023F and 0330-033F
0240-024F and 0340-034F
0250-025F and 0350-035F
0260-026F and 0360-036F
0270-027F and 0370-037F
----------P035A035B--------------------------
PORT 035A-035B - Adaptec AH1520 jumper settings
035A R I/O channel setup (see #P106)
035B R transfer mode setup (see #P107)
Bitfields for Adaptec AH1520 channel setup jumper settings:
Bit(s) Description (Table P106)
7 SCSI parity disabled
6-5 DMA channel (00 = channel 0, 01 = 5, 10 = 6, 11 = 7)
4-3 IRQ number (00 = IRQ9, 01 = IRQ10, 10 = IRQ11, 11 = IRQ12)
2-0 SCSI ID
SeeAlso: #P107
Bitfields for Adaptec AH1520 transfer mode setup jumper settings:
Bit(s) Description (Table P107)
7 DMA transfer mode (clear for PIO)
6 boot enabled
5-4 boot type
00 ???
01 boot from floppy
10 print configured options
11 boot from hard disk
3 enable sync negotiation
2 enable target disconnection
1-0 unused???
SeeAlso: #P106
----------P035F------------------------------
PORT 035F - ARTEC Handyscanner A400Z. alternate address at 15F.
----------P03600367--------------------------
PORT 0360-0367 - PC network (XT only)
----------P0360036F--------------------------
PORT 0360-036F - PC network (AT)
----------P0360036F--------------------------
PORT 0360-036F - National Semiconductor DP8390(1)C/NS3249C network chipset
Note: cards based on this IEEE 802.3 networking chipset can use any range
of 16 consecutive addresses, and provide a total of four pages of
sixteen registers (see #P108,#P109,#P110,#P141)
(Table P108)
Values for NS DP8390C/NS3249C network chipset Page 0 registers:
Number Read Register Write Register
00h Command reg. (see #P112) CR Command reg. CR
01h current local DMA address 0 CLDA0 page start reg. PSTART
02h current local DMA address 1 CLDA1 page stop reg. PSTOP
03h boundary pointer BNRY boundary pointer BNRY
04h transmit status reg. TSR Tx page start address TPSR
05h number of collisions reg. NCR Tx byte count reg.0 TBCR0
06h FIFO Tx byte count reg.1 TBCR1
07h interrupt status reg. ISR interrupt status reg. ISR
08h current remote DMA address 0 CRDA0 remote start addr.reg.0 RSAR0
09h current remote DMA address 1 CRDA1 remote start addr.reg.1 RSAR1
0Ah reserved remote byte count reg.0 RBCR0
0Bh reserved remote byte count reg.1 RBCR1
0Ch receive status reg. RSR Rx configuration reg. RCR
0Dh tally counter 0 (frame errors) CNTR0 Tx configuration reg. TCR
0Eh tally counter 1 (CRC errors) CNTR1 data configuration reg. DCR
0Fh tally counter 2 (missed pkt) CNTR2 interrupt mask reg. IMR
SeeAlso: #P109,#P110,#P111
(Table P109)
Values for NS DP8390C/NS3249C network chipset Page 1 registers:
Number Read/Write
00h Command CR (see #P112)
01h physical address reg.0 PAR0
02h physical address reg.1 PAR1
03h physical address reg.2 PAR2
04h physical address reg.3 PAR3
05h physical address reg.4 PAR4
06h physical address reg.5 PAR5
07h current page reg. CURR
08h multicast address reg.0 MAR0
09h multicast address reg.1 MAR1
0Ah multicast address reg.2 MAR2
0Bh multicast address reg.3 MAR3
0Ch multicast address reg.4 MAR4
0Dh multicast address reg.5 MAR5
0Eh multicast address reg.6 MAR6
0Fh multicast address reg.7 MAR7
SeeAlso: #P108,#P110,#P111
(Table P110)
Values for NS DP8390C/NS3249C network chipset Page 2 registers:
Number Read Register Write Register
00h Command CR Command CR
01h page start reg. PSTART current local DMA addr.0 CLDA0
02h page stop reg. BPSTOP current local DMA addr.1 CLDA1
03h remote next packet pointer remote next packet pointer
04h Tx page start address TPSR reserved
05h local next packet pointer local next packet pointer
06h address counter (upper) address counter (upper)
07h address counter (lower) address counter (lower)
08h reserved reserved
09h reserved reserved
0Ah reserved reserved
0Bh reserved reserved
0Ch Rx configuration reg. RCR reserved
0Dh Tx configuration reg. TCR reserved
0Eh data configuration reg. DCR reserved
0Fh interrupt mask reg. IMR reserved
Note: this is a diagnostics page, and should never be modfied under normal
operation.
SeeAlso: #P108,#P109,#P111
(Table P111)
Values for NS DP8390C/NS3249C network chipset Page 3 registers:
Number Read Register Write Register
00h Command CR (see #P112) Command CR
Note: Test Page - should never be modified!
SeeAlso: #P108,#P109,#P110
Bitfields for NS DP8390C/NS3249C network chipset command register (00h):
Bit(s) Description (Table P112)
0 software reset command (1=offline, 0=online)
1 do not activate NIC after reset command
2 start transmision of a packet
3-5 remote DMA command
000 not allowed
001 remote read
010 remote write
011 send packet
1xx abort/complete rmote DMA
6-7 page select
00 register page 0
01 register page 1
10 register page 2
11 register page 3
SeeAlso: #P111
----------P036B------------------------------
PORT 036B - GI1904 Scanner Interface Adapter
Range: PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh
Range: PORT 03ABh, PORT 03EBh
----------P03700377--------------------------
PORT 0370-0377 - FDC 2 (2nd Floppy Disk Controller) first FDC at 03F0
Note: floppy disk controller is usually an 8272, 8272A, NEC765 (or
compatible), or an 82072 or 82077AA for perpendicular recording at
2.88M
SeeAlso: PORT 03F0h-03F7h
0370 R diskette Extra High Density controller board jumpers (AT)
0370 R diskette controller status A (PS/2, PS/2 model 30)
0371 R diskette controller status B (PS/2, PS/2 model 30)
0372 W diskette controller DOR (Digital Output Register)
0374 R diskette controller main status register
0374 W diskette controller datarate select register
0375 RW diskette controller command/data register
0376 RW (2nd FIXED disk controller status/data register)
0377 RW (2nd FIXED disk controller drive address register)
0377 R diskette controller DIR (Digital Input Register)
0377 W select register for diskette data transfer rate
----------P0378------------------------------
PORT 0378 - Covox 'Speech Thing' COMPATIBLE SPEECH OUTPUT
SeeAlso: PORT 022Fh"mc-soundmachine",PORT 0388h-038Fh"soundmachine"
0378 W speech output via printer port
(with mc-soundmachine, enabled if bit4=1 in 38F)
----------P0378037A--------------------------
PORT 0378-037A - parallel printer port, same as 0278 and 03BC
0378 W data port
0379 RW status port
037A RW control port
037B ?? bit 7: shadow RAM on/off (UniRAM adapter,according to c't 7/90)
----------P0380038F--------------------------
PORT 0380-038F - 2nd BSC (Binary Synchronous Communication) adapter
SeeAlso: PORT 03A0h"BSC"
----------P0380038C--------------------------
PORT 0380-038C - 2nd SDLC (Synchronous Data Link Control) adapter
Notes: Initialization of the SDLC adapter is performed in a typical
sequence like this: Setup 8255 port A-C configuration by writing
98h to 383h, followed by initializing 8255 port C by writing 0Dh
to 382h. Reset 8273 internal registers by pulsing 8255 port B4.
After this the 8253 has to be programmed to the desired values
(counter 0 in mode 3). Now the 8273 is ready to be configured for
the operating mode that defines the communication environment in
which it will be used.
Note on 8273: Each 8273 protocol controllers internal register is
programmed by individual set/reset commands (via 388h) in
conjunction with a parameter (via 389h) that give an OR/AND mask
to the internal register value.
Although the 8273 is a full duplex device, there is only one
command register. Thus, the command register must be used for
only one command sequence at a time and the transmitter and
receiver may never be simultaneously in a command phase.
The system software starts the command phase by writing a command
byte into the command register. If further information is required
by the 8273 prior to execution of the command, the system software
must write the list of parameters into the parameter register.
SeeAlso: PORT 03A0h"SDLC"
0380 R on adapter 8255(A5) port A: internal/external sensing (see #P113)
0381 W on adapter 8255(A5) port B: external modem interface (see #P114)
0382 RW on adapter 8255(A5) port C: internal control (see #P115)
0383 ?W on adapter 8255(A5) mode initialization
0384 RW on adapter 8253 (programmable counter) counter 0:
LSB / MSB square wave generator (input for timer 2, connected
to 8255 bitC5)
0385 RW on adapter 8253 counter 1: LSB / MSB inactivity time-outs
(connected to 8255 bitA7, IRQ4 level)
0386 RW on adapter 8253 counter 2: LSB / MSB inactivity time-outs
(connected to 8255 bitA6, IRQ4 level)
0387 ?W on adapter 8253 mode register (see #P116)
0388 R on adapter 8273 status register (see #P117)
0388 W on adapter 8273 command register (see #P118)
0389 R on adapter 8273 (immediate) result register (see #P125)
0389 W on adapter 8273 parameter register
Commands issued via PORT 0388h may need additional parameters,
which have to be passed through this port (see table).
038A R on adapter 8273 transmit INT status (DMA/INT)
038A W on adapter 8274 reset
038B R on adapter 8273 receive INT status (DMA/INT)
038C W on adapter 8273 data: direct program control (DPC)
scratch-pad
Bitfields for SDLC 8255 port A:
Bit(s) Description (Table P113)
7 =1 timer 1 output active
6 =1 timer 2 output active
5 =1 modem status changed
4 receive clock active (if pulsing)
3 =0 clear to send is on from interface
2 transmit clock active (if pulsing)
1 =0 data carrier detect is on from interface
0 =0 ring indicator is on from interface
SeeAlso: #P114,#P115
Bitfields for SDLC 8255 port B:
Bit(s) Description (Table P114)
7 enable IRQ 4 level interrupt
6 =1 gate timer 1
5 =1 gate timer 2
4 =1 reset 8273
3 =1 reset modem status changed logic
2 =0 turn on test
1 =0 turn on select standby at modem interface
0 =0 turn on data signal rate select at modem interface
SeeAlso: #P113,#P115
Bitfields for SDLC 8255 port C:
Bit(s) Description (Table P115)
7 R- =? not used (detection: =1 SDLC, =0 may be SDLC or BSC??)
6 R- =0 test indicate active
5 R- timer 0 output (if pulsing)
4 R- receive data (if pulsing)
3 -W =0 gate interrupts 3 and 4
2 -W =1 electronic wrap
1 -W =1 gate external clock
0 -W =1 gate internal clock
SeeAlso: #P113,#P114
Bitfields for SDLC 8253 mode register:
Bit(s) Description (Table P116)
7-6 SC1-SC0 00, 01, 10= select counter 0,1,2; 11=illegal
5-4 RL1-RL0 00= couner latching operation
01= read/load most significant byte (MSB)
10= read/load least significant byte (LSB)
11= read/load LSB first, then MSB
3-1 M2-M0 000= mode 0
001= mode 1
x10= mode 2
x11= mode 3
100= mode 4
101= mode 5
0 BCD 0= binary counter 16bits
1= BCD counter 4 decades
Bitfields for SDLC 8273 status register:
Bit(s) Description (Table P117)
7 =1 command busy (CBSY)
6 =1 command buffer full (CBF)
5 =1 command parameter buffer full (CPBF)
4 =1 command result buffer full (CRBF)
3 =1 Rx interupt (RxINT)
2 =1 Tx interupt (TxINT)
1 =1 RxINT result available (RxIRA)
0 =1 TxINT result available (TxIRA)
SeeAlso: #P118
(Table P118)
Values for SDCL 8273 command register:
commands: parameters: results: result port: int:
A4: set one-bit delay set mask - - no
64: reset one-bit delay reset mask - - no
97: set data transfer set mask - - no
57: reset data transfer reset mask - - no
91: set operating mode set mask - - no
51: reset operating mode reset mask - - no
A0: set serial I/O mode set mask - - no
60: reset serial I/O mode reset mask - - no
C0: general receive B0,B1 RIC,R0,R1,A,C RXI/R yes
C1: selective receive B0,B1,A1,A2 RIC,RD,R1,A,C RXI/R yes
C5: receive disable - - - no
C8: transmit frame L0, L1, A, C TIC TXI/R yes
C9: transmit transparent L0, L1 TIC TXI/R yes
CC: abort transmit frame - TIC TXI/R yes
CD: abort transmit - TIC TXI/R yes
22: read 8273 port A - port value result no
23: read 8273 port B - port value result no
A3: set 8273 port A bit set mask - - no
63: set 8273 port B bit reset mask - - no
Notes: B0/B1 LSB/MSB of the receiver buffer length
L0/L1 LSB/MSB of the Tx buffer length
A1/A2 receive frame address match field one/two
A address fieldof received frame. In non-buffered mode, this
result is not provided.
C control field of received frame. In non-buffered mode, this
result is not provided.
RXI/R TXI/R receive/transmit interrupt result register
R0/R1 LBS/MSB of the length of the frame received
RIC/TIC receiver/transmitter interrupt result code
SeeAlso: #P119,#P120,#P121,#P122,#P123,#P124
Bitfields for SDLC 8273 interal port A: Modem Control Input Port:
Bit(s) Description (Table P119)
7-5 not used
4 DSR change (PA4)
3 CTS change (PA3)
2 Data Set Ready (PA2)
1 Carrier Detect (PA1)
0 Clear to Send (PA0)
SeeAlso: #P118
Bitfields for SDLC 8273 interal port B: Modem Control Output Port:
Bit(s) Description (Table P120)
7-6 not used
5 Flag Detect (PB5)
4-3 reserved
2 Data Terminal Ready (PB2)
1 reserved (PB1)
0 Request to Send (PB0)
SeeAlso: #P118
Bitfields for SDLC 8273 internal: Operating Mode Register:
Bit(s) Description (Table P121)
7-6 not used
5 =1 HDLC abort enable
4 =1 EOP interrupt enable
3 =1 enable early Tx interrupt
2 =1 Buffered Mode
1 =1 Two Preframe Sync Characters
0 =1 Flag Stream Mode
SeeAlso: #P118
Bitfields for SDLC 8273 internal: Serial I/O Register:
Bit(s) Description (Table P122)
7-3 not used
2 =1 Data Loopback
1 =1 Clock Loopback
0 =1 NRZI Mode
SeeAlso: #P118
Bitfields for SDLC 8273 internal: Data Transfer Mode Register:
Bit(s) Description (Table P123)
7-1 not used
0 =1 Interrupt Data Transfers
SeeAlso: #P118
Bitfields for SDLC 8273 internal: One-Bit Delay Mode Register:
Bit(s) Description (Table P124)
7 =1 One-Bit Delay Enable
6-0 not used
SeeAlso: #P118
(Table P125)
Values for SDLC 8273 result register:
transmit result codes: status after interrupt:
0C: early transmit interrupt transmitter active
0D: frame transmit complete idle or flags
0E: DMA underrun abort
0F: clear to send error abort
10: abort complete idle or flags
receive result codes:
X0: A1 match / general receive active
X1: A2 match active
03: CRC error active
04: abort detected active
05: idle detected disabled
06: EOP detected disabled
07: frame less than 32 bits active
08: DMA overrun disabled
09: memory buffer overflow disabled
0A: carrier detect failure disabled
0B: receiver interrupt overrun disabled
X bits received inlast byte:
E: all eight bits of last byte (bit7-0)
0: bit0 only
8: bit1-0
4: bit2-0
C: bit3-0
2: bit4-0
A: bit5-0
6: bit6-0
----------P03880389--------------------------
PORT 0388-0389 - AdLib - MONO SOUND OUTPUT
Note: also supported by SoundBlaster and compatibles
SeeAlso: PORT 0220h-0223h,PORT 0388h-038Fh"soundmachine"
0388 R both speakers -- Status
bit7 : interrupt request (IRQ)
bit6 : timer 1 overflow
bit5 : timer 2 overflow
bit4-0: reserved
0388 W both speakers -- Address port (see #P126)
index in OPL2 (YMF3812), OPL3 (YMF262), OPL4 (YF278-F)
0389 W data port
Note: the AdLib requires a delay of 3.3 microseconds between writing to
PORT 0388h and writing to PORT 0389h, and a delay of 23 microseconds
after a write to PORT 0389h before any other operation is allowed
(Table P126)
Values for AdLib address port index:
01h Enable waveform control
bit 7-6: (OPL4, OPL3 in OPL2 mode only) lsi test
bit 5: (OPL2 only) wave select enable (WS)
(OPL4, OPL3) lsi test
bit 4-0: lsi test
02h Timer #1 data (OPL2 and OPL3 in OPL2 mode only)
03h Timer #2 data (OPL2 and OPL3 in OPL2 mode only)
04h Timer control flags (OPL2 and OPL3 in OPL2 mode only)
bit 7 : reset interrupt (RST)
bit 6 : timer 1 mask (MASK1)
bit 5 : timer 2 mask (MASK2)
bit 4-2: reserved
bit 1 : start timer 2 (ST2)
bit 0 : start timer 1 (ST1)
04h (OPL3 in OPL3 mode only) connection select
bit 7-6: reserved
bit 5-0: connection selection
05h (OPL3) compatibility register
bit 7-1: reserved
bit 0: enable OPL3 mode (NEW), default disabled
08h Speech synthesis mode
bit 7: (OPL2 only) speech synthesis or FM music mode (CSM)
bit 6: select keyboard split point (SEL/NTS)
bit 5-0: reserved
20h-35h Amplitude Modulation / Vibrato
bit 7: AM modulation (AM)
bit 6: vibrato (VIB)
bit 5: sustain (EG)
bit 4: keyboard scaling rate (KSR)
bit 3-0: multi (MF)
40h-55h Level key scaling / Total level
bit 7-6: key scale level (KSL)
bit 5-0: total level (TL)
60h-75h Attack / Decay rate
bit 7-4: attack rate
bit 3-0: decay rate
80h-95h Sustain / Release rate
bit 7-4: sustain level
bit 3-0: release rate
A0h-A8h Octave / Frequency (LSB)
A9h-AFh ???
B0h-B8h Octave / Frequency Number
bit 7-6: reserved
bit 5 : key on, mute
bit 4-2: block, octave
bit 1-0: f-number (MSB)
BDh percussion, vibrato, AM (OPL2, OPL3 in OPL2 mode only)
bit 7: amplitude modulation (AM)
bit 6: vibrato (VIB)
bit 5: ryhthm, percussion on/off (R)
bit 4: bass drum on/off (BD)
bit 3: snare drum on/off (SD)
bit 2: tom-tom on/off (TOM)
bit 1: top cymbal on/off (TC)
bit 0: hi hat on/off (HH)
C0h-C8h Feedback / Algorithm
bit 7-4: OPL3: channel D-A
bit 3-1: feedback
bit 0: connection
E0h-F5h Waveform Selection
bit 7-3: reserved
bit 2 : (OPL3) waveform bit2
bit 1-0: waveform
SeeAlso: #P127
(Table P127)
Values for Sound Blaster registers inside groups:
Offset
+00..+02: operators 1-3 modulator channel 1-3
+03..+05: operators 4-6 carrier channel 1-3
+08..+0A: operators 7-9 modulator channel 4-6
+0B..+0D: operators 10-12 carrier channel 4-6
+10..+12: operators 13-15 modulator channel 7-9
+13..+15: operators 16-18 carrier channel 7-9
+06, +07, +0E, +0F: reserved
SeeAlso: #P126
----------P03880389--------------------------
PORT 0388-0389 ---- Soundblaster PRO FM-Chip
----------P0388038B--------------------------
PORT 0388-038B ---- Soundblaster 16 ASP FM-Chip
----------P0388038F--------------------------
PORT 0388-038F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note: Adlib-compatible, Covox 'voice master' & 'speech thing' compatible
soundcard
SeeAlso: PORT 022Fh"soundmachine",PORT 0278h"Covox"
0388 W Covox 'speech thing'compatible speech output via printer port?
enabled if bit 6 set in PORT 038Fh
0388 RW Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
(see PORT 0388h-0389h"Sound Blaster")
0389 W Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
(see PORT 0388h-0389h"Sound Blaster")
038A W IıC control for TDA7302 NF-MUX and X24C04 EEPROM
bit 7: IıC bus SDA out (data), enabled if bit2=1 in PORT 038Fh
bit 0: IıC bus SCL out (clock), enabled if bit2=1 in PORT 038Fh
038B R IıC status for TDA7302 NF-MUX and X24C04 EEPROM
bit 7: IıC bus SDA in (data), enabled if bit2=1 in PORT 038Fh
bit 0: IıC bus SCL in (clock), enabled if bit2=1 in PORT 038Fh
038F RW configuration port (power on default=0, all features disabled)
(see #P128)
Bitfields for mc-soundmachine configuration port:
Bit(s) Description (Table P128)
7 Covox 'voice master' enabled at PORT 022Fh
6 "" 'speech thing' enabled at PORT 03BCh
5 "" enabled at PORT 0278h
4 "" enabled at PORT 0378h
3 not used (0388???)
2 IıC bus enabled (see PORT 038Ah,PORT 038Bh)
1 gameport enabled (see PORT 0201h)
0 AdLib registers (see PORT 0388h,PORT 0389h) enabled
----------P03900397--------------------------
PORT 0390-0397 - Sunshine EW-901B, EW-904B
EPROM writer card for EPROMs up to 27512
0390-0393 ?? adresses of the 8255 on the EW-90xB
----------P0390039F--------------------------
PORT 0390-039F - Cluster adapter (AT)
0390 ?? (adapter 0) (XT)
0391 ?? (adapter 0) (XT)
0392 ?? (adapter 0) (XT)
0393 ?? (adapter 0) (XT)
----------P03980399--------------------------
PORT 0398-0399 - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 026Eh
0398 W index for data port
0399 RW EPP command data
----------