Here are some examples, with answers entered by other users.<br>
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<table><tr><td><img src=sessions/1-1010-355-1.jpg><img src=sessions/1-1010-355-2.jpg></td>
<td>an inverter
<br>an inverter
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1029-346-1.jpg><img src=sessions/1-1029-346-2.jpg></td>
<td>a lone transistor with logic elements around it (may or may not have an asterix)
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1055-403-1.jpg><img src=sessions/1-1055-403-2.jpg></td>
<td>a box with "D2" in it
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1064-354-1.jpg><img src=sessions/1-1064-354-2.jpg></td>
<td>an inverter
<br>an inverter
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1077-543-1.jpg><img src=sessions/1-1077-543-2.jpg></td>
<td>an inverter
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1084-345-1.jpg><img src=sessions/1-1084-345-2.jpg></td>
<td>a lone transistor with logic elements around it (may or may not have an asterix)
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1097-579-1.jpg><img src=sessions/1-1097-579-2.jpg></td>
<td>2 input NOR gate
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1119-354-1.jpg><img src=sessions/1-1119-354-2.jpg></td>
<td>3 input NOR gate
<br>3 input NOR gate
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1122-557-1.jpg><img src=sessions/1-1122-557-2.jpg></td>
<td>2 input AND gate
<br>2 input AND gate
<br></td></td></table><hr>
<table><tr><td><img src=sessions/1-1130-577-1.jpg><img src=sessions/1-1130-577-2.jpg></td>
<td>2 input NOR gate
<br></td></td></table><hr>